base.cc (10028:fb8c44de891a) base.cc (10052:5bb8e054456b)
1/*
2 * Copyright (c) 2013 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 46 unchanged lines hidden (view full) ---

55#include "mem/cache/base.hh"
56#include "mem/request.hh"
57#include "sim/system.hh"
58
59BasePrefetcher::BasePrefetcher(const Params *p)
60 : ClockedObject(p), size(p->size), latency(p->latency), degree(p->degree),
61 useMasterId(p->use_master_id), pageStop(!p->cross_pages),
62 serialSquash(p->serial_squash), onlyData(p->data_accesses_only),
1/*
2 * Copyright (c) 2013 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 46 unchanged lines hidden (view full) ---

55#include "mem/cache/base.hh"
56#include "mem/request.hh"
57#include "sim/system.hh"
58
59BasePrefetcher::BasePrefetcher(const Params *p)
60 : ClockedObject(p), size(p->size), latency(p->latency), degree(p->degree),
61 useMasterId(p->use_master_id), pageStop(!p->cross_pages),
62 serialSquash(p->serial_squash), onlyData(p->data_accesses_only),
63 system(p->sys), masterId(system->getMasterId(name()))
63 onMissOnly(p->on_miss_only), onReadOnly(p->on_read_only),
64 onPrefetch(p->on_prefetch), system(p->sys),
65 masterId(system->getMasterId(name()))
64{
65}
66
67void
68BasePrefetcher::setCache(BaseCache *_cache)
69{
70 cache = _cache;
71 blkSize = cache->getBlockSize();

--- 108 unchanged lines hidden (view full) ---

180 pkt->isSecure() ? "s" : "ns");
181 return pkt;
182}
183
184
185Tick
186BasePrefetcher::notify(PacketPtr &pkt, Tick tick)
187{
66{
67}
68
69void
70BasePrefetcher::setCache(BaseCache *_cache)
71{
72 cache = _cache;
73 blkSize = cache->getBlockSize();

--- 108 unchanged lines hidden (view full) ---

182 pkt->isSecure() ? "s" : "ns");
183 return pkt;
184}
185
186
187Tick
188BasePrefetcher::notify(PacketPtr &pkt, Tick tick)
189{
188 if (!pkt->req->isUncacheable() && !(pkt->req->isInstFetch() && onlyData)) {
190 // Don't consult the prefetcher if any of the following conditons are true
191 // 1) The request is uncacheable
192 // 2) The request is a fetch, but we are only prefeching data
193 // 3) The request is a cache hit, but we are only training on misses
194 // 4) THe request is a write, but we are only training on reads
195 if (!pkt->req->isUncacheable() && !(pkt->req->isInstFetch() && onlyData) &&
196 !(onMissOnly && inCache(pkt->getAddr(), true)) &&
197 !(onReadOnly && !pkt->isRead())) {
189 // Calculate the blk address
190 Addr blk_addr = pkt->getAddr() & ~(Addr)(blkSize-1);
191 bool is_secure = pkt->isSecure();
192
193 // Check if miss is in pfq, if so remove it
194 std::list<DeferredPacket>::iterator iter = inPrefetch(blk_addr,
195 is_secure);
196 if (iter != pf.end()) {

--- 60 unchanged lines hidden (view full) ---

257 prefetchReq->setFlags(Request::SECURE);
258 prefetchReq->taskId(ContextSwitchTaskId::Prefetcher);
259 PacketPtr prefetch =
260 new Packet(prefetchReq, MemCmd::HardPFReq);
261 prefetch->allocate();
262 prefetch->req->setThreadContext(pkt->req->contextId(),
263 pkt->req->threadId());
264
198 // Calculate the blk address
199 Addr blk_addr = pkt->getAddr() & ~(Addr)(blkSize-1);
200 bool is_secure = pkt->isSecure();
201
202 // Check if miss is in pfq, if so remove it
203 std::list<DeferredPacket>::iterator iter = inPrefetch(blk_addr,
204 is_secure);
205 if (iter != pf.end()) {

--- 60 unchanged lines hidden (view full) ---

266 prefetchReq->setFlags(Request::SECURE);
267 prefetchReq->taskId(ContextSwitchTaskId::Prefetcher);
268 PacketPtr prefetch =
269 new Packet(prefetchReq, MemCmd::HardPFReq);
270 prefetch->allocate();
271 prefetch->req->setThreadContext(pkt->req->contextId(),
272 pkt->req->threadId());
273
274 // Tag orefetch reqeuests with corresponding PC to train lower
275 // cache-level prefetchers
276 if (onPrefetch && pkt->req->hasPC())
277 prefetch->req->setPC(pkt->req->getPC());
278
265 // We just remove the head if we are full
266 if (pf.size() == size) {
267 pfRemovedFull++;
268 PacketPtr old_pkt = pf.begin()->pkt;
269 DPRINTF(HWPrefetch, "Prefetch queue full, "
270 "removing oldest 0x%x\n", old_pkt->getAddr());
271 delete old_pkt->req;
272 delete old_pkt;

--- 32 unchanged lines hidden --- 		279 // We just remove the head if we are full
280 if (pf.size() == size) {
281 pfRemovedFull++;
282 PacketPtr old_pkt = pf.begin()->pkt;
283 DPRINTF(HWPrefetch, "Prefetch queue full, "
284 "removing oldest 0x%x\n", old_pkt->getAddr());
285 delete old_pkt->req;
286 delete old_pkt;

--- 32 unchanged lines hidden ---