1/* 2 * Copyright (c) 2013-2014 ARM Limited 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 42 unchanged lines hidden (view full) --- 51#include <cassert> 52 53#include "base/intmath.hh" 54#include "cpu/base.hh" 55#include "mem/cache/base.hh" 56#include "params/BasePrefetcher.hh" 57#include "sim/system.hh" 58 |
59BasePrefetcher::PrefetchInfo::PrefetchInfo(PacketPtr pkt, Addr addr, bool miss) |
60 : address(addr), pc(pkt->req->hasPC() ? pkt->req->getPC() : 0), 61 masterId(pkt->req->masterId()), validPC(pkt->req->hasPC()), |
62 secure(pkt->isSecure()), size(pkt->req->getSize()), write(pkt->isWrite()), 63 paddress(pkt->req->getPaddr()), cacheMiss(miss) |
64{ |
65 unsigned int req_size = pkt->req->getSize(); 66 if (!write && miss) { 67 data = nullptr; 68 } else { 69 data = new uint8_t[req_size]; 70 Addr offset = pkt->req->getPaddr() - pkt->getAddr(); 71 std::memcpy(data, &(pkt->getConstPtr<uint8_t>()[offset]), req_size); 72 } |
73} 74 75BasePrefetcher::PrefetchInfo::PrefetchInfo(PrefetchInfo const &pfi, Addr addr) 76 : address(addr), pc(pfi.pc), masterId(pfi.masterId), validPC(pfi.validPC), |
77 secure(pfi.secure), size(pfi.size), write(pfi.write), 78 paddress(pfi.paddress), cacheMiss(pfi.cacheMiss), data(nullptr) |
79{ 80} 81 82void 83BasePrefetcher::PrefetchListener::notify(const PacketPtr &pkt) 84{ 85 if (isFill) { 86 parent.notifyFill(pkt); 87 } else { |
88 parent.probeNotify(pkt, miss); |
89 } 90} 91 92BasePrefetcher::BasePrefetcher(const BasePrefetcherParams *p) 93 : ClockedObject(p), listeners(), cache(nullptr), blkSize(p->block_size), 94 lBlkSize(floorLog2(blkSize)), onMiss(p->on_miss), onRead(p->on_read), 95 onWrite(p->on_write), onData(p->on_data), onInst(p->on_inst), 96 masterId(p->sys->getMasterId(this)), pageBytes(p->sys->getPageBytes()), --- 22 unchanged lines hidden (view full) --- 119 pfIssued 120 .name(name() + ".num_hwpf_issued") 121 .desc("number of hwpf issued") 122 ; 123 124} 125 126bool |
127BasePrefetcher::observeAccess(const PacketPtr &pkt, bool miss) const |
128{ |
129 bool fetch = pkt->req->isInstFetch(); 130 bool read = pkt->isRead(); 131 bool inv = pkt->isInvalidate(); |
132 133 if (pkt->req->isUncacheable()) return false; 134 if (fetch && !onInst) return false; 135 if (!fetch && !onData) return false; 136 if (!fetch && read && !onRead) return false; 137 if (!fetch && !read && !onWrite) return false; 138 if (!fetch && !read && inv) return false; 139 if (pkt->cmd == MemCmd::CleanEvict) return false; 140 141 if (onMiss) { |
142 return miss; |
143 } 144 145 return true; 146} 147 148bool 149BasePrefetcher::inCache(Addr addr, bool is_secure) const 150{ --- 44 unchanged lines hidden (view full) --- 195 196Addr 197BasePrefetcher::pageIthBlockAddress(Addr page, uint32_t blockIndex) const 198{ 199 return page + (blockIndex << lBlkSize); 200} 201 202void |
203BasePrefetcher::probeNotify(const PacketPtr &pkt, bool miss) |
204{ 205 // Don't notify prefetcher on SWPrefetch, cache maintenance 206 // operations or for writes that we are coaslescing. 207 if (pkt->cmd.isSWPrefetch()) return; 208 if (pkt->req->isCacheMaintenance()) return; 209 if (pkt->isWrite() && cache != nullptr && cache->coalesce()) return; |
210 if (!pkt->req->hasPaddr()) { 211 panic("Request must have a physical address"); 212 } |
213 214 if (hasBeenPrefetched(pkt->getAddr(), pkt->isSecure())) { 215 usefulPrefetches += 1; 216 } 217 218 // Verify this access type is observed by prefetcher |
219 if (observeAccess(pkt, miss)) { |
220 if (useVirtualAddresses && pkt->req->hasVaddr()) { |
221 PrefetchInfo pfi(pkt, pkt->req->getVaddr(), miss); |
222 notify(pkt, pfi); |
223 } else if (!useVirtualAddresses) { 224 PrefetchInfo pfi(pkt, pkt->req->getPaddr(), miss); |
225 notify(pkt, pfi); 226 } 227 } 228} 229 230void 231BasePrefetcher::regProbeListeners() 232{ 233 /** 234 * If no probes were added by the configuration scripts, connect to the 235 * parent cache using the probe "Miss". Also connect to "Hit", if the 236 * cache is configured to prefetch on accesses. 237 */ 238 if (listeners.empty() && cache != nullptr) { 239 ProbeManager *pm(cache->getProbeManager()); |
240 listeners.push_back(new PrefetchListener(*this, pm, "Miss", false, 241 true)); 242 listeners.push_back(new PrefetchListener(*this, pm, "Fill", true, 243 false)); |
244 if (prefetchOnAccess) { |
245 listeners.push_back(new PrefetchListener(*this, pm, "Hit", false, 246 false)); |
247 } 248 } 249} 250 251void 252BasePrefetcher::addEventProbe(SimObject *obj, const char *name) 253{ 254 ProbeManager *pm(obj->getProbeManager()); 255 listeners.push_back(new PrefetchListener(*this, pm, name)); 256} |