53a54
> #include "cpu/base.hh"
57a59,64
> void
> BasePrefetcher::PrefetchListener::notify(const PacketPtr &pkt)
> {
> parent.probeNotify(pkt);
> }
>
59c66
< : ClockedObject(p), cache(nullptr), blkSize(0), lBlkSize(0),
---
> : ClockedObject(p), listeners(), cache(nullptr), blkSize(0), lBlkSize(0),
63c70,71
< pageBytes(system->getPageBytes())
---
> pageBytes(system->getPageBytes()),
> prefetchOnAccess(p->prefetch_on_access)
165a174,208
>
> void
> BasePrefetcher::probeNotify(const PacketPtr &pkt)
> {
> // Don't notify prefetcher on SWPrefetch, cache maintenance
> // operations or for writes that we are coaslescing.
> if (pkt->cmd.isSWPrefetch()) return;
> if (pkt->req->isCacheMaintenance()) return;
> if (pkt->isWrite() && cache != nullptr && cache->coalesce()) return;
> notify(pkt);
> }
>
> void
> BasePrefetcher::regProbeListeners()
> {
> /**
> * If no probes were added by the configuration scripts, connect to the
> * parent cache using the probe "Miss". Also connect to "Hit", if the
> * cache is configured to prefetch on accesses.
> */
> if (listeners.empty() && cache != nullptr) {
> ProbeManager *pm(cache->getProbeManager());
> listeners.push_back(new PrefetchListener(*this, pm, "Miss"));
> if (prefetchOnAccess) {
> listeners.push_back(new PrefetchListener(*this, pm, "Hit"));
> }
> }
> }
>
> void
> BasePrefetcher::addEventProbe(SimObject *obj, const char *name)
> {
> ProbeManager *pm(obj->getProbeManager());
> listeners.push_back(new PrefetchListener(*this, pm, name));
> }