1/*
2 * Copyright (c) 2013-2014 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Ron Dreslinski
41 * Mitch Hayenga
42 */
43
44/**
45 * @file
46 * Hardware Prefetcher Definition.
47 */
48
49#include "mem/cache/prefetch/base.hh"
50
51#include <cassert>
52
53#include "base/intmath.hh"
| 1/*
2 * Copyright (c) 2013-2014 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Ron Dreslinski
41 * Mitch Hayenga
42 */
43
44/**
45 * @file
46 * Hardware Prefetcher Definition.
47 */
48
49#include "mem/cache/prefetch/base.hh"
50
51#include <cassert>
52
53#include "base/intmath.hh"
|
| 54#include "cpu/base.hh"
|
54#include "mem/cache/base.hh"
55#include "params/BasePrefetcher.hh"
56#include "sim/system.hh"
57
| 55#include "mem/cache/base.hh"
56#include "params/BasePrefetcher.hh"
57#include "sim/system.hh"
58
|
| 59void
60BasePrefetcher::PrefetchListener::notify(const PacketPtr &pkt)
61{
62 parent.probeNotify(pkt);
63}
64
|
58BasePrefetcher::BasePrefetcher(const BasePrefetcherParams *p)
| 65BasePrefetcher::BasePrefetcher(const BasePrefetcherParams *p)
|
59 : ClockedObject(p), cache(nullptr), blkSize(0), lBlkSize(0),
| 66 : ClockedObject(p), listeners(), cache(nullptr), blkSize(0), lBlkSize(0),
|
60 system(p->sys), onMiss(p->on_miss), onRead(p->on_read),
61 onWrite(p->on_write), onData(p->on_data), onInst(p->on_inst),
62 masterId(system->getMasterId(this)),
| 67 system(p->sys), onMiss(p->on_miss), onRead(p->on_read),
68 onWrite(p->on_write), onData(p->on_data), onInst(p->on_inst),
69 masterId(system->getMasterId(this)),
|
63 pageBytes(system->getPageBytes())
| 70 pageBytes(system->getPageBytes()),
71 prefetchOnAccess(p->prefetch_on_access)
|
64{
65}
66
67void
68BasePrefetcher::setCache(BaseCache *_cache)
69{
70 assert(!cache);
71 cache = _cache;
72 blkSize = cache->getBlockSize();
73 lBlkSize = floorLog2(blkSize);
74}
75
76void
77BasePrefetcher::regStats()
78{
79 ClockedObject::regStats();
80
81 pfIssued
82 .name(name() + ".num_hwpf_issued")
83 .desc("number of hwpf issued")
84 ;
85
86}
87
88bool
89BasePrefetcher::observeAccess(const PacketPtr &pkt) const
90{
91 Addr addr = pkt->getAddr();
92 bool fetch = pkt->req->isInstFetch();
93 bool read = pkt->isRead();
94 bool inv = pkt->isInvalidate();
95 bool is_secure = pkt->isSecure();
96
97 if (pkt->req->isUncacheable()) return false;
98 if (fetch && !onInst) return false;
99 if (!fetch && !onData) return false;
100 if (!fetch && read && !onRead) return false;
101 if (!fetch && !read && !onWrite) return false;
102 if (!fetch && !read && inv) return false;
103 if (pkt->cmd == MemCmd::CleanEvict) return false;
104
105 if (onMiss) {
106 return !inCache(addr, is_secure) &&
107 !inMissQueue(addr, is_secure);
108 }
109
110 return true;
111}
112
113bool
114BasePrefetcher::inCache(Addr addr, bool is_secure) const
115{
116 if (cache->inCache(addr, is_secure)) {
117 return true;
118 }
119 return false;
120}
121
122bool
123BasePrefetcher::inMissQueue(Addr addr, bool is_secure) const
124{
125 if (cache->inMissQueue(addr, is_secure)) {
126 return true;
127 }
128 return false;
129}
130
131bool
132BasePrefetcher::samePage(Addr a, Addr b) const
133{
134 return roundDown(a, pageBytes) == roundDown(b, pageBytes);
135}
136
137Addr
138BasePrefetcher::blockAddress(Addr a) const
139{
140 return a & ~(blkSize-1);
141}
142
143Addr
144BasePrefetcher::blockIndex(Addr a) const
145{
146 return a >> lBlkSize;
147}
148
149Addr
150BasePrefetcher::pageAddress(Addr a) const
151{
152 return roundDown(a, pageBytes);
153}
154
155Addr
156BasePrefetcher::pageOffset(Addr a) const
157{
158 return a & (pageBytes - 1);
159}
160
161Addr
162BasePrefetcher::pageIthBlockAddress(Addr page, uint32_t blockIndex) const
163{
164 return page + (blockIndex << lBlkSize);
165}
| 72{
73}
74
75void
76BasePrefetcher::setCache(BaseCache *_cache)
77{
78 assert(!cache);
79 cache = _cache;
80 blkSize = cache->getBlockSize();
81 lBlkSize = floorLog2(blkSize);
82}
83
84void
85BasePrefetcher::regStats()
86{
87 ClockedObject::regStats();
88
89 pfIssued
90 .name(name() + ".num_hwpf_issued")
91 .desc("number of hwpf issued")
92 ;
93
94}
95
96bool
97BasePrefetcher::observeAccess(const PacketPtr &pkt) const
98{
99 Addr addr = pkt->getAddr();
100 bool fetch = pkt->req->isInstFetch();
101 bool read = pkt->isRead();
102 bool inv = pkt->isInvalidate();
103 bool is_secure = pkt->isSecure();
104
105 if (pkt->req->isUncacheable()) return false;
106 if (fetch && !onInst) return false;
107 if (!fetch && !onData) return false;
108 if (!fetch && read && !onRead) return false;
109 if (!fetch && !read && !onWrite) return false;
110 if (!fetch && !read && inv) return false;
111 if (pkt->cmd == MemCmd::CleanEvict) return false;
112
113 if (onMiss) {
114 return !inCache(addr, is_secure) &&
115 !inMissQueue(addr, is_secure);
116 }
117
118 return true;
119}
120
121bool
122BasePrefetcher::inCache(Addr addr, bool is_secure) const
123{
124 if (cache->inCache(addr, is_secure)) {
125 return true;
126 }
127 return false;
128}
129
130bool
131BasePrefetcher::inMissQueue(Addr addr, bool is_secure) const
132{
133 if (cache->inMissQueue(addr, is_secure)) {
134 return true;
135 }
136 return false;
137}
138
139bool
140BasePrefetcher::samePage(Addr a, Addr b) const
141{
142 return roundDown(a, pageBytes) == roundDown(b, pageBytes);
143}
144
145Addr
146BasePrefetcher::blockAddress(Addr a) const
147{
148 return a & ~(blkSize-1);
149}
150
151Addr
152BasePrefetcher::blockIndex(Addr a) const
153{
154 return a >> lBlkSize;
155}
156
157Addr
158BasePrefetcher::pageAddress(Addr a) const
159{
160 return roundDown(a, pageBytes);
161}
162
163Addr
164BasePrefetcher::pageOffset(Addr a) const
165{
166 return a & (pageBytes - 1);
167}
168
169Addr
170BasePrefetcher::pageIthBlockAddress(Addr page, uint32_t blockIndex) const
171{
172 return page + (blockIndex << lBlkSize);
173}
|
| 174
175void
176BasePrefetcher::probeNotify(const PacketPtr &pkt)
177{
178 // Don't notify prefetcher on SWPrefetch, cache maintenance
179 // operations or for writes that we are coaslescing.
180 if (pkt->cmd.isSWPrefetch()) return;
181 if (pkt->req->isCacheMaintenance()) return;
182 if (pkt->isWrite() && cache != nullptr && cache->coalesce()) return;
183 notify(pkt);
184}
185
186void
187BasePrefetcher::regProbeListeners()
188{
189 /**
190 * If no probes were added by the configuration scripts, connect to the
191 * parent cache using the probe "Miss". Also connect to "Hit", if the
192 * cache is configured to prefetch on accesses.
193 */
194 if (listeners.empty() && cache != nullptr) {
195 ProbeManager *pm(cache->getProbeManager());
196 listeners.push_back(new PrefetchListener(*this, pm, "Miss"));
197 if (prefetchOnAccess) {
198 listeners.push_back(new PrefetchListener(*this, pm, "Hit"));
199 }
200 }
201}
202
203void
204BasePrefetcher::addEventProbe(SimObject *obj, const char *name)
205{
206 ProbeManager *pm(obj->getProbeManager());
207 listeners.push_back(new PrefetchListener(*this, pm, name));
208}
|
| |