1/*
2 * Copyright (c) 2013-2014 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Ron Dreslinski
41 * Mitch Hayenga
42 */
43
44/**
45 * @file
46 * Hardware Prefetcher Definition.
47 */
48
49#include <list>
50
51#include "base/intmath.hh"
52#include "mem/cache/prefetch/base.hh"
53#include "mem/cache/base.hh"
54#include "sim/system.hh"
55
56BasePrefetcher::BasePrefetcher(const BasePrefetcherParams *p)
57 : ClockedObject(p), cache(nullptr), blkSize(0), lBlkSize(0),
58 system(p->sys), onMiss(p->on_miss), onRead(p->on_read),
59 onWrite(p->on_write), onData(p->on_data), onInst(p->on_inst),
60 masterId(system->getMasterId(name())),
61 pageBytes(system->getPageBytes())
62{
63}
64
65void
66BasePrefetcher::setCache(BaseCache *_cache)
67{
68 assert(!cache);
69 cache = _cache;
70 blkSize = cache->getBlockSize();
71 lBlkSize = floorLog2(blkSize);
72}
73
74void
75BasePrefetcher::regStats()
76{
77 ClockedObject::regStats();
78
79 pfIssued
80 .name(name() + ".num_hwpf_issued")
81 .desc("number of hwpf issued")
82 ;
83
84}
85
86bool
87BasePrefetcher::observeAccess(const PacketPtr &pkt) const
88{
89 Addr addr = pkt->getAddr();
90 bool fetch = pkt->req->isInstFetch();
91 bool read = pkt->isRead();
92 bool inv = pkt->isInvalidate();
93 bool is_secure = pkt->isSecure();
94
95 if (pkt->req->isUncacheable()) return false;
96 if (fetch && !onInst) return false;
97 if (!fetch && !onData) return false;
98 if (!fetch && read && !onRead) return false;
99 if (!fetch && !read && !onWrite) return false;
100 if (!fetch && !read && inv) return false;
101 if (pkt->cmd == MemCmd::CleanEvict) return false;
102
103 if (onMiss) {
104 return !inCache(addr, is_secure) &&
105 !inMissQueue(addr, is_secure);
106 }
107
108 return true;
109}
110
111bool
112BasePrefetcher::inCache(Addr addr, bool is_secure) const
113{
114 if (cache->inCache(addr, is_secure)) {
115 return true;
116 }
117 return false;
118}
119
120bool
121BasePrefetcher::inMissQueue(Addr addr, bool is_secure) const
122{
123 if (cache->inMissQueue(addr, is_secure)) {
124 return true;
125 }
126 return false;
127}
128
129bool
130BasePrefetcher::samePage(Addr a, Addr b) const
131{
132 return roundDown(a, pageBytes) == roundDown(b, pageBytes);
133}
134
135Addr
136BasePrefetcher::blockAddress(Addr a) const
137{
138 return a & ~(blkSize-1);
139}
140
141Addr
142BasePrefetcher::blockIndex(Addr a) const
143{
144 return a >> lBlkSize;
145}
146
147Addr
148BasePrefetcher::pageAddress(Addr a) const
149{
150 return roundDown(a, pageBytes);
151}
152
153Addr
154BasePrefetcher::pageOffset(Addr a) const
155{
156 return a & (pageBytes - 1);
157}
158
159Addr
160BasePrefetcher::pageIthBlockAddress(Addr page, uint32_t blockIndex) const
161{
162 return page + (blockIndex << lBlkSize);
163}