1/*
2 * Copyright (c) 2013-2014 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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76}
77
78BasePrefetcher::BasePrefetcher(const BasePrefetcherParams *p)
79 : ClockedObject(p), listeners(), cache(nullptr), blkSize(p->block_size),
80 lBlkSize(floorLog2(blkSize)), onMiss(p->on_miss), onRead(p->on_read),
81 onWrite(p->on_write), onData(p->on_data), onInst(p->on_inst),
82 masterId(p->sys->getMasterId(this)), pageBytes(p->sys->getPageBytes()),
83 prefetchOnAccess(p->prefetch_on_access),
84 useVirtualAddresses(p->use_virtual_addresses)
85{
86}
87
88void
89BasePrefetcher::setCache(BaseCache *_cache)
90{
91 assert(!cache);
92 cache = _cache;

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141
142bool
143BasePrefetcher::inMissQueue(Addr addr, bool is_secure) const
144{
145 return cache->inMissQueue(addr, is_secure);
146}
147
148bool
149BasePrefetcher::samePage(Addr a, Addr b) const
150{
151 return roundDown(a, pageBytes) == roundDown(b, pageBytes);
152}
153
154Addr
155BasePrefetcher::blockAddress(Addr a) const
156{

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185BasePrefetcher::probeNotify(const PacketPtr &pkt)
186{
187 // Don't notify prefetcher on SWPrefetch, cache maintenance
188 // operations or for writes that we are coaslescing.
189 if (pkt->cmd.isSWPrefetch()) return;
190 if (pkt->req->isCacheMaintenance()) return;
191 if (pkt->isWrite() && cache != nullptr && cache->coalesce()) return;
192
193 // Verify this access type is observed by prefetcher
194 if (observeAccess(pkt)) {
195 if (useVirtualAddresses && pkt->req->hasVaddr()) {
196 PrefetchInfo pfi(pkt, pkt->req->getVaddr());
197 notify(pkt, pfi);
198 } else if (!useVirtualAddresses && pkt->req->hasPaddr()) {
199 PrefetchInfo pfi(pkt, pkt->req->getPaddr());
200 notify(pkt, pfi);

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