1/*
2 * Copyright (c) 2013 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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55#include "mem/cache/base.hh"
56#include "mem/request.hh"
57#include "sim/system.hh"
58
59BasePrefetcher::BasePrefetcher(const Params *p)
60 : ClockedObject(p), size(p->size), latency(p->latency), degree(p->degree),
61 useMasterId(p->use_master_id), pageStop(!p->cross_pages),
62 serialSquash(p->serial_squash), onlyData(p->data_accesses_only),
63 system(p->sys), masterId(system->getMasterId(name()))
64{
65}
66
67void
68BasePrefetcher::setCache(BaseCache *_cache)
69{
70 cache = _cache;
71 blkSize = cache->getBlockSize();

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180 pkt->isSecure() ? "s" : "ns");
181 return pkt;
182}
183
184
185Tick
186BasePrefetcher::notify(PacketPtr &pkt, Tick tick)
187{
188 if (!pkt->req->isUncacheable() && !(pkt->req->isInstFetch() && onlyData)) {
189 // Calculate the blk address
190 Addr blk_addr = pkt->getAddr() & ~(Addr)(blkSize-1);
191 bool is_secure = pkt->isSecure();
192
193 // Check if miss is in pfq, if so remove it
194 std::list<DeferredPacket>::iterator iter = inPrefetch(blk_addr,
195 is_secure);
196 if (iter != pf.end()) {

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257 prefetchReq->setFlags(Request::SECURE);
258 prefetchReq->taskId(ContextSwitchTaskId::Prefetcher);
259 PacketPtr prefetch =
260 new Packet(prefetchReq, MemCmd::HardPFReq);
261 prefetch->allocate();
262 prefetch->req->setThreadContext(pkt->req->contextId(),
263 pkt->req->threadId());
264
265 // We just remove the head if we are full
266 if (pf.size() == size) {
267 pfRemovedFull++;
268 PacketPtr old_pkt = pf.begin()->pkt;
269 DPRINTF(HWPrefetch, "Prefetch queue full, "
270 "removing oldest 0x%x\n", old_pkt->getAddr());
271 delete old_pkt->req;
272 delete old_pkt;

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