1/*
2 * Copyright (c) 2013 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 108 unchanged lines hidden (view full) ---

117 pfSquashed
118 .name(name() + ".prefetcher.num_hwpf_squashed_from_miss")
119 .desc("number of hwpf that got squashed due to a miss "
120 "aborting calculation time")
121 ;
122}
123
124inline bool
125BasePrefetcher::inCache(Addr addr)
126{
127 if (cache->inCache(addr)) {
128 pfCacheHit++;
129 return true;
130 }
131 return false;
132}
133
134inline bool
135BasePrefetcher::inMissQueue(Addr addr)
136{
137 if (cache->inMissQueue(addr)) {
138 pfMSHRHit++;
139 return true;
140 }
141 return false;
142}
143
144PacketPtr
145BasePrefetcher::getPacket()

--- 6 unchanged lines hidden (view full) ---

152 }
153
154 PacketPtr pkt = pf.begin()->pkt;
155 while (!pf.empty()) {
156 pkt = pf.begin()->pkt;
157 pf.pop_front();
158
159 Addr blk_addr = pkt->getAddr() & ~(Addr)(blkSize-1);
160
161 if (!inCache(blk_addr) && !inMissQueue(blk_addr))
162 // we found a prefetch, return it
163 break;
164
165 DPRINTF(HWPrefetch, "addr 0x%x in cache, skipping\n", pkt->getAddr());
166 delete pkt->req;
167 delete pkt;
168
169 if (pf.empty()) {
170 cache->deassertMemSideBusRequest(BaseCache::Request_PF);
171 return NULL; // None left, all were in cache
172 }
173 }
174
175 pfIssued++;
176 assert(pkt != NULL);
177 DPRINTF(HWPrefetch, "returning 0x%x\n", pkt->getAddr());
178 return pkt;
179}
180
181
182Tick
183BasePrefetcher::notify(PacketPtr &pkt, Tick tick)
184{
185 if (!pkt->req->isUncacheable() && !(pkt->req->isInstFetch() && onlyData)) {
186 // Calculate the blk address
187 Addr blk_addr = pkt->getAddr() & ~(Addr)(blkSize-1);
188
189 // Check if miss is in pfq, if so remove it
190 std::list<DeferredPacket>::iterator iter = inPrefetch(blk_addr);
191 if (iter != pf.end()) {
192 DPRINTF(HWPrefetch, "Saw a miss to a queued prefetch addr: "
193 "0x%x, removing it\n", blk_addr);
194 pfRemovedMSHR++;
195 delete iter->pkt->req;
196 delete iter->pkt;
197 iter = pf.erase(iter);
198 if (pf.empty())
199 cache->deassertMemSideBusRequest(BaseCache::Request_PF);
200 }
201

--- 32 unchanged lines hidden (view full) ---

234
235 pfIdentified++;
236
237 DPRINTF(HWPrefetch, "Found a pf candidate addr: 0x%x, "
238 "inserting into prefetch queue with delay %d time %d\n",
239 addr, *delayIter, time);
240
241 // Check if it is already in the pf buffer
242 if (inPrefetch(addr) != pf.end()) {
243 pfBufferHit++;
244 DPRINTF(HWPrefetch, "Prefetch addr already in pf buffer\n");
245 continue;
246 }
247
248 // create a prefetch memreq
249 Request *prefetchReq = new Request(*addrIter, blkSize, 0, masterId);
250 prefetchReq->taskId(ContextSwitchTaskId::Prefetcher);
251 PacketPtr prefetch =
252 new Packet(prefetchReq, MemCmd::HardPFReq);
253 prefetch->allocate();
254 prefetch->req->setThreadContext(pkt->req->contextId(),
255 pkt->req->threadId());
256
257 // We just remove the head if we are full

--- 11 unchanged lines hidden (view full) ---

269 prefetch));
270 }
271 }
272
273 return pf.empty() ? 0 : pf.front().tick;
274}
275
276std::list<BasePrefetcher::DeferredPacket>::iterator
277BasePrefetcher::inPrefetch(Addr address)
278{
279 // Guaranteed to only be one match, we always check before inserting
280 std::list<DeferredPacket>::iterator iter;
281 for (iter = pf.begin(); iter != pf.end(); iter++) {
282 if ((iter->pkt->getAddr() & ~(Addr)(blkSize-1)) == address) {
283 return iter;
284 }
285 }
286 return pf.end();
287}
288
289bool
290BasePrefetcher::samePage(Addr a, Addr b)
291{
292 return roundDown(a, TheISA::VMPageSize) == roundDown(b, TheISA::VMPageSize);
293}
294
295