1/*
2 * Copyright (c) 2013 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Ron Dreslinski
41 */
42
43/**
44 * @file
45 * Hardware Prefetcher Definition.
46 */
47
48#include <list>
49
50#include "arch/isa_traits.hh"
51#include "base/trace.hh"
52#include "config/the_isa.hh"
53#include "debug/HWPrefetch.hh"
54#include "mem/cache/prefetch/base.hh"
55#include "mem/cache/base.hh"
56#include "mem/request.hh"
57#include "sim/system.hh"
58
59BasePrefetcher::BasePrefetcher(const Params *p)
60 : ClockedObject(p), size(p->size), latency(p->latency), degree(p->degree),
61 useMasterId(p->use_master_id), pageStop(!p->cross_pages),
62 serialSquash(p->serial_squash), onlyData(p->data_accesses_only),
63 system(p->sys), masterId(system->getMasterId(name()))
64{
65}
66
67void
68BasePrefetcher::setCache(BaseCache *_cache)
69{
70 cache = _cache;
71 blkSize = cache->getBlockSize();
72}
73
74void
75BasePrefetcher::regStats()
76{
77 pfIdentified
78 .name(name() + ".prefetcher.num_hwpf_identified")
79 .desc("number of hwpf identified")
80 ;
81
82 pfMSHRHit
83 .name(name() + ".prefetcher.num_hwpf_already_in_mshr")
84 .desc("number of hwpf that were already in mshr")
85 ;
86
87 pfCacheHit
88 .name(name() + ".prefetcher.num_hwpf_already_in_cache")
89 .desc("number of hwpf that were already in the cache")
90 ;
91
92 pfBufferHit
93 .name(name() + ".prefetcher.num_hwpf_already_in_prefetcher")
94 .desc("number of hwpf that were already in the prefetch queue")
95 ;
96
97 pfRemovedFull
98 .name(name() + ".prefetcher.num_hwpf_evicted")
99 .desc("number of hwpf removed due to no buffer left")
100 ;
101
102 pfRemovedMSHR
103 .name(name() + ".prefetcher.num_hwpf_removed_MSHR_hit")
104 .desc("number of hwpf removed because MSHR allocated")
105 ;
106
107 pfIssued
108 .name(name() + ".prefetcher.num_hwpf_issued")
109 .desc("number of hwpf issued")
110 ;
111
112 pfSpanPage
113 .name(name() + ".prefetcher.num_hwpf_span_page")
114 .desc("number of hwpf spanning a virtual page")
115 ;
116
117 pfSquashed
118 .name(name() + ".prefetcher.num_hwpf_squashed_from_miss")
119 .desc("number of hwpf that got squashed due to a miss "
120 "aborting calculation time")
121 ;
122}
123
124inline bool
125BasePrefetcher::inCache(Addr addr)
126{
127 if (cache->inCache(addr)) {
128 pfCacheHit++;
129 return true;
130 }
131 return false;
132}
133
134inline bool
135BasePrefetcher::inMissQueue(Addr addr)
136{
137 if (cache->inMissQueue(addr)) {
138 pfMSHRHit++;
139 return true;
140 }
141 return false;
142}
143
144PacketPtr
145BasePrefetcher::getPacket()
146{
147 DPRINTF(HWPrefetch, "Requesting a hw_pf to issue\n");
148
149 if (pf.empty()) {
150 DPRINTF(HWPrefetch, "No HW_PF found\n");
151 return NULL;
152 }
153
154 PacketPtr pkt = pf.begin()->pkt;
155 while (!pf.empty()) {
156 pkt = pf.begin()->pkt;
157 pf.pop_front();
158
159 Addr blk_addr = pkt->getAddr() & ~(Addr)(blkSize-1);
160
161 if (!inCache(blk_addr) && !inMissQueue(blk_addr))
162 // we found a prefetch, return it
163 break;
164
165 DPRINTF(HWPrefetch, "addr 0x%x in cache, skipping\n", pkt->getAddr());
166 delete pkt->req;
167 delete pkt;
168
169 if (pf.empty()) {
170 cache->deassertMemSideBusRequest(BaseCache::Request_PF);
171 return NULL; // None left, all were in cache
172 }
173 }
174
175 pfIssued++;
176 assert(pkt != NULL);
177 DPRINTF(HWPrefetch, "returning 0x%x\n", pkt->getAddr());
178 return pkt;
179}
180
181
182Tick
183BasePrefetcher::notify(PacketPtr &pkt, Tick tick)
184{
185 if (!pkt->req->isUncacheable() && !(pkt->req->isInstFetch() && onlyData)) {
186 // Calculate the blk address
187 Addr blk_addr = pkt->getAddr() & ~(Addr)(blkSize-1);
188
189 // Check if miss is in pfq, if so remove it
190 std::list<DeferredPacket>::iterator iter = inPrefetch(blk_addr);
191 if (iter != pf.end()) {
192 DPRINTF(HWPrefetch, "Saw a miss to a queued prefetch addr: "
193 "0x%x, removing it\n", blk_addr);
194 pfRemovedMSHR++;
195 delete iter->pkt->req;
196 delete iter->pkt;
197 iter = pf.erase(iter);
198 if (pf.empty())
199 cache->deassertMemSideBusRequest(BaseCache::Request_PF);
200 }
201
202 // Remove anything in queue with delay older than time
203 // since everything is inserted in time order, start from end
204 // and work until pf.empty() or time is earlier
205 // This is done to emulate Aborting the previous work on a new miss
206 // Needed for serial calculators like GHB
207 if (serialSquash) {
208 iter = pf.end();
209 if (iter != pf.begin())
210 iter--;
211 while (!pf.empty() && iter->tick >= tick) {
212 pfSquashed++;
213 DPRINTF(HWPrefetch, "Squashing old prefetch addr: 0x%x\n",
214 iter->pkt->getAddr());
215 delete iter->pkt->req;
216 delete iter->pkt;
217 iter = pf.erase(iter);
218 if (iter != pf.begin())
219 iter--;
220 }
221 if (pf.empty())
222 cache->deassertMemSideBusRequest(BaseCache::Request_PF);
223 }
224
225
226 std::list<Addr> addresses;
227 std::list<Cycles> delays;
228 calculatePrefetch(pkt, addresses, delays);
229
230 std::list<Addr>::iterator addrIter = addresses.begin();
231 std::list<Cycles>::iterator delayIter = delays.begin();
232 for (; addrIter != addresses.end(); ++addrIter, ++delayIter) {
233 Addr addr = *addrIter;
234
235 pfIdentified++;
236
237 DPRINTF(HWPrefetch, "Found a pf candidate addr: 0x%x, "
238 "inserting into prefetch queue with delay %d time %d\n",
239 addr, *delayIter, time);
240
241 // Check if it is already in the pf buffer
242 if (inPrefetch(addr) != pf.end()) {
243 pfBufferHit++;
244 DPRINTF(HWPrefetch, "Prefetch addr already in pf buffer\n");
245 continue;
246 }
247
248 // create a prefetch memreq
249 Request *prefetchReq = new Request(*addrIter, blkSize, 0, masterId);
250 PacketPtr prefetch =
251 new Packet(prefetchReq, MemCmd::HardPFReq);
252 prefetch->allocate();
253 prefetch->req->setThreadContext(pkt->req->contextId(),
254 pkt->req->threadId());
255
256 // We just remove the head if we are full
257 if (pf.size() == size) {
258 pfRemovedFull++;
259 PacketPtr old_pkt = pf.begin()->pkt;
260 DPRINTF(HWPrefetch, "Prefetch queue full, "
261 "removing oldest 0x%x\n", old_pkt->getAddr());
262 delete old_pkt->req;
263 delete old_pkt;
264 pf.pop_front();
265 }
266
267 pf.push_back(DeferredPacket(tick + clockPeriod() * *delayIter,
268 prefetch));
269 }
270 }
271
272 return pf.empty() ? 0 : pf.front().tick;
273}
274
275std::list<BasePrefetcher::DeferredPacket>::iterator
276BasePrefetcher::inPrefetch(Addr address)
277{
278 // Guaranteed to only be one match, we always check before inserting
279 std::list<DeferredPacket>::iterator iter;
280 for (iter = pf.begin(); iter != pf.end(); iter++) {
281 if ((iter->pkt->getAddr() & ~(Addr)(blkSize-1)) == address) {
282 return iter;
283 }
284 }
285 return pf.end();
286}
287
288bool
289BasePrefetcher::samePage(Addr a, Addr b)
290{
291 return roundDown(a, TheISA::VMPageSize) == roundDown(b, TheISA::VMPageSize);
292}
293
294