Prefetcher.py (10466:73b7549d979e) Prefetcher.py (10623:b9646f4546ad)
1# Copyright (c) 2012 ARM Limited
1# Copyright (c) 2012, 2014 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated

--- 22 unchanged lines hidden (view full) ---

32# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
33# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
34# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
35# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
36# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
37# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38#
39# Authors: Ron Dreslinski
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated

--- 22 unchanged lines hidden (view full) ---

32# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
33# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
34# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
35# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
36# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
37# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38#
39# Authors: Ron Dreslinski
40# Mitch Hayenga
40
41from ClockedObject import ClockedObject
42from m5.params import *
43from m5.proxy import *
44
45class BasePrefetcher(ClockedObject):
46 type = 'BasePrefetcher'
47 abstract = True
48 cxx_header = "mem/cache/prefetch/base.hh"
41
42from ClockedObject import ClockedObject
43from m5.params import *
44from m5.proxy import *
45
46class BasePrefetcher(ClockedObject):
47 type = 'BasePrefetcher'
48 abstract = True
49 cxx_header = "mem/cache/prefetch/base.hh"
49 size = Param.Int(100,
50 "Number of entries in the hardware prefetch queue")
51 cross_pages = Param.Bool(False,
52 "Allow prefetches to cross virtual page boundaries")
53 serial_squash = Param.Bool(False,
54 "Squash prefetches with a later time on a subsequent miss")
55 degree = Param.Int(1,
56 "Degree of the prefetch depth")
57 latency = Param.Cycles('1', "Latency of the prefetcher")
58 use_master_id = Param.Bool(True,
59 "Use the master id to separate calculations of prefetches")
60 data_accesses_only = Param.Bool(False,
61 "Only prefetch on data not on instruction accesses")
62 on_miss_only = Param.Bool(False,
63 "Only prefetch on miss (as opposed to always)")
64 on_read_only = Param.Bool(False,
65 "Only prefetch on read requests (write requests ignored)")
66 on_prefetch = Param.Bool(True,
67 "Let lower cache prefetcher train on prefetch requests")
68 inst_tagged = Param.Bool(True,
69 "Perform a tagged prefetch for instruction fetches always")
70 sys = Param.System(Parent.any, "System this prefetcher belongs to")
71
50 sys = Param.System(Parent.any, "System this prefetcher belongs to")
51
72class StridePrefetcher(BasePrefetcher):
52 on_miss = Param.Bool(False, "Only notify prefetcher on misses")
53 on_read = Param.Bool(True, "Notify prefetcher on reads")
54 on_write = Param.Bool(True, "Notify prefetcher on writes")
55 on_data = Param.Bool(True, "Notify prefetcher on data accesses")
56 on_inst = Param.Bool(True, "Notify prefetcher on instruction accesses")
57
58class QueuedPrefetcher(BasePrefetcher):
59 type = "QueuedPrefetcher"
60 abstract = True
61 cxx_class = "QueuedPrefetcher"
62 cxx_header = "mem/cache/prefetch/queued.hh"
63 latency = Param.Int(1, "Latency for generated prefetches")
64 queue_size = Param.Int(32, "Maximum number of queued prefetches")
65 queue_squash = Param.Bool(True, "Squash queued prefetch on demand access")
66 queue_filter = Param.Bool(True, "Don't queue redundant prefetches")
67 cache_snoop = Param.Bool(False, "Snoop cache to eliminate redundant request")
68
69 tag_prefetch = Param.Bool(True, "Tag prefetch with PC of generating access")
70
71class StridePrefetcher(QueuedPrefetcher):
73 type = 'StridePrefetcher'
74 cxx_class = 'StridePrefetcher'
75 cxx_header = "mem/cache/prefetch/stride.hh"
76
72 type = 'StridePrefetcher'
73 cxx_class = 'StridePrefetcher'
74 cxx_header = "mem/cache/prefetch/stride.hh"
75
77class TaggedPrefetcher(BasePrefetcher):
76 max_conf = Param.Int(7, "Maximum confidence level")
77 thresh_conf = Param.Int(4, "Threshold confidence level")
78 min_conf = Param.Int(0, "Minimum confidence level")
79 start_conf = Param.Int(4, "Starting confidence for new entries")
80
81 table_sets = Param.Int(16, "Number of sets in PC lookup table")
82 table_assoc = Param.Int(4, "Associativity of PC lookup table")
83 use_master_id = Param.Bool(True, "Use master id based history")
84
85 degree = Param.Int(4, "Number of prefetches to generate")
86
87class TaggedPrefetcher(QueuedPrefetcher):
78 type = 'TaggedPrefetcher'
79 cxx_class = 'TaggedPrefetcher'
80 cxx_header = "mem/cache/prefetch/tagged.hh"
81
88 type = 'TaggedPrefetcher'
89 cxx_class = 'TaggedPrefetcher'
90 cxx_header = "mem/cache/prefetch/tagged.hh"
91
82
83
84
92 degree = Param.Int(2, "Number of prefetches to generate")