1from m5.SimObject import SimObject 2from m5.params import *
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3from m5.proxy import * 4 |
5class BasePrefetcher(SimObject): 6 type = 'BasePrefetcher' 7 abstract = True 8 size = Param.Int(100, 9 "Number of entries in the hardware prefetch queue") 10 cross_pages = Param.Bool(False, 11 "Allow prefetches to cross virtual page boundaries") 12 serial_squash = Param.Bool(False, 13 "Squash prefetches with a later time on a subsequent miss") 14 degree = Param.Int(1, 15 "Degree of the prefetch depth") 16 latency = Param.Latency('10t', 17 "Latency of the prefetcher")
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16 use_cpu_id = Param.Bool(True,
17 "Use the CPU ID to separate calculations of prefetches")
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18 use_master_id = Param.Bool(True, 19 "Use the master id to separate calculations of prefetches") |
20 data_accesses_only = Param.Bool(False, 21 "Only prefetch on data not on instruction accesses")
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22 sys = Param.System(Parent.any, "System this device belongs to") |
23 24class GHBPrefetcher(BasePrefetcher): 25 type = 'GHBPrefetcher' 26 cxx_class = 'GHBPrefetcher' 27 28class StridePrefetcher(BasePrefetcher): 29 type = 'StridePrefetcher' 30 cxx_class = 'StridePrefetcher' 31 32class TaggedPrefetcher(BasePrefetcher): 33 type = 'TaggedPrefetcher' 34 cxx_class = 'TaggedPrefetcher' 35 36 37 38
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