1# Copyright (c) 2012, 2014 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated
10# unmodified and in its entirety in all distributions of the software,
11# modified or unmodified, in source code or in binary form.
12#
13# Copyright (c) 2005 The Regents of The University of Michigan
14# All rights reserved.
15#
16# Redistribution and use in source and binary forms, with or without
17# modification, are permitted provided that the following conditions are
18# met: redistributions of source code must retain the above copyright
19# notice, this list of conditions and the following disclaimer;
20# redistributions in binary form must reproduce the above copyright
21# notice, this list of conditions and the following disclaimer in the
22# documentation and/or other materials provided with the distribution;
23# neither the name of the copyright holders nor the names of its
24# contributors may be used to endorse or promote products derived from
25# this software without specific prior written permission.
26#
27# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
30# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
31# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
32# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
33# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
34# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
35# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
36# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
37# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38#
39# Authors: Ron Dreslinski
40# Mitch Hayenga
41
42from ClockedObject import ClockedObject
43from m5.SimObject import *
44from m5.params import *
45from m5.proxy import *
46
47class HWPProbeEvent(object):
48 def __init__(self, prefetcher, obj, *listOfNames):
49 self.obj = obj
50 self.prefetcher = prefetcher
51 self.names = listOfNames
52
53 def register(self):
54 if self.obj:
55 for name in self.names:
56 self.prefetcher.getCCObject().addEventProbe(
57 self.obj.getCCObject(), name)
58
59class BasePrefetcher(ClockedObject):
60 type = 'BasePrefetcher'
61 abstract = True
62 cxx_header = "mem/cache/prefetch/base.hh"
63 cxx_exports = [
64 PyBindMethod("addEventProbe"),
65 ]
66 sys = Param.System(Parent.any, "System this prefetcher belongs to")
67
| 1# Copyright (c) 2012, 2014 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated
10# unmodified and in its entirety in all distributions of the software,
11# modified or unmodified, in source code or in binary form.
12#
13# Copyright (c) 2005 The Regents of The University of Michigan
14# All rights reserved.
15#
16# Redistribution and use in source and binary forms, with or without
17# modification, are permitted provided that the following conditions are
18# met: redistributions of source code must retain the above copyright
19# notice, this list of conditions and the following disclaimer;
20# redistributions in binary form must reproduce the above copyright
21# notice, this list of conditions and the following disclaimer in the
22# documentation and/or other materials provided with the distribution;
23# neither the name of the copyright holders nor the names of its
24# contributors may be used to endorse or promote products derived from
25# this software without specific prior written permission.
26#
27# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
30# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
31# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
32# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
33# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
34# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
35# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
36# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
37# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38#
39# Authors: Ron Dreslinski
40# Mitch Hayenga
41
42from ClockedObject import ClockedObject
43from m5.SimObject import *
44from m5.params import *
45from m5.proxy import *
46
47class HWPProbeEvent(object):
48 def __init__(self, prefetcher, obj, *listOfNames):
49 self.obj = obj
50 self.prefetcher = prefetcher
51 self.names = listOfNames
52
53 def register(self):
54 if self.obj:
55 for name in self.names:
56 self.prefetcher.getCCObject().addEventProbe(
57 self.obj.getCCObject(), name)
58
59class BasePrefetcher(ClockedObject):
60 type = 'BasePrefetcher'
61 abstract = True
62 cxx_header = "mem/cache/prefetch/base.hh"
63 cxx_exports = [
64 PyBindMethod("addEventProbe"),
65 ]
66 sys = Param.System(Parent.any, "System this prefetcher belongs to")
67
|
| 68 # Get the block size from the parent (system)
69 block_size = Param.Int(Parent.cache_line_size, "Block size in bytes")
70
|
68 on_miss = Param.Bool(False, "Only notify prefetcher on misses")
69 on_read = Param.Bool(True, "Notify prefetcher on reads")
70 on_write = Param.Bool(True, "Notify prefetcher on writes")
71 on_data = Param.Bool(True, "Notify prefetcher on data accesses")
72 on_inst = Param.Bool(True, "Notify prefetcher on instruction accesses")
73 prefetch_on_access = Param.Bool(Parent.prefetch_on_access,
74 "Notify the hardware prefetcher on every access (not just misses)")
75
76 _events = []
77 def addEvent(self, newObject):
78 self._events.append(newObject)
79
80 # Override the normal SimObject::regProbeListeners method and
81 # register deferred event handlers.
82 def regProbeListeners(self):
83 for event in self._events:
84 event.register()
85 self.getCCObject().regProbeListeners()
86
87 def listenFromProbe(self, simObj, *probeNames):
88 if not isinstance(simObj, SimObject):
89 raise TypeError("argument must be of SimObject type")
90 if len(probeNames) <= 0:
91 raise TypeError("probeNames must have at least one element")
92 self.addEvent(HWPProbeEvent(self, simObj, *probeNames))
93
94class QueuedPrefetcher(BasePrefetcher):
95 type = "QueuedPrefetcher"
96 abstract = True
97 cxx_class = "QueuedPrefetcher"
98 cxx_header = "mem/cache/prefetch/queued.hh"
99 latency = Param.Int(1, "Latency for generated prefetches")
100 queue_size = Param.Int(32, "Maximum number of queued prefetches")
101 queue_squash = Param.Bool(True, "Squash queued prefetch on demand access")
102 queue_filter = Param.Bool(True, "Don't queue redundant prefetches")
103 cache_snoop = Param.Bool(False, "Snoop cache to eliminate redundant request")
104
105 tag_prefetch = Param.Bool(True, "Tag prefetch with PC of generating access")
106
107class StridePrefetcher(QueuedPrefetcher):
108 type = 'StridePrefetcher'
109 cxx_class = 'StridePrefetcher'
110 cxx_header = "mem/cache/prefetch/stride.hh"
111
| 71 on_miss = Param.Bool(False, "Only notify prefetcher on misses")
72 on_read = Param.Bool(True, "Notify prefetcher on reads")
73 on_write = Param.Bool(True, "Notify prefetcher on writes")
74 on_data = Param.Bool(True, "Notify prefetcher on data accesses")
75 on_inst = Param.Bool(True, "Notify prefetcher on instruction accesses")
76 prefetch_on_access = Param.Bool(Parent.prefetch_on_access,
77 "Notify the hardware prefetcher on every access (not just misses)")
78
79 _events = []
80 def addEvent(self, newObject):
81 self._events.append(newObject)
82
83 # Override the normal SimObject::regProbeListeners method and
84 # register deferred event handlers.
85 def regProbeListeners(self):
86 for event in self._events:
87 event.register()
88 self.getCCObject().regProbeListeners()
89
90 def listenFromProbe(self, simObj, *probeNames):
91 if not isinstance(simObj, SimObject):
92 raise TypeError("argument must be of SimObject type")
93 if len(probeNames) <= 0:
94 raise TypeError("probeNames must have at least one element")
95 self.addEvent(HWPProbeEvent(self, simObj, *probeNames))
96
97class QueuedPrefetcher(BasePrefetcher):
98 type = "QueuedPrefetcher"
99 abstract = True
100 cxx_class = "QueuedPrefetcher"
101 cxx_header = "mem/cache/prefetch/queued.hh"
102 latency = Param.Int(1, "Latency for generated prefetches")
103 queue_size = Param.Int(32, "Maximum number of queued prefetches")
104 queue_squash = Param.Bool(True, "Squash queued prefetch on demand access")
105 queue_filter = Param.Bool(True, "Don't queue redundant prefetches")
106 cache_snoop = Param.Bool(False, "Snoop cache to eliminate redundant request")
107
108 tag_prefetch = Param.Bool(True, "Tag prefetch with PC of generating access")
109
110class StridePrefetcher(QueuedPrefetcher):
111 type = 'StridePrefetcher'
112 cxx_class = 'StridePrefetcher'
113 cxx_header = "mem/cache/prefetch/stride.hh"
114
|
| 115 # Do not consult stride prefetcher on instruction accesses
116 on_inst = False
117
|
112 max_conf = Param.Int(7, "Maximum confidence level")
113 thresh_conf = Param.Int(4, "Threshold confidence level")
114 min_conf = Param.Int(0, "Minimum confidence level")
115 start_conf = Param.Int(4, "Starting confidence for new entries")
116
117 table_sets = Param.Int(16, "Number of sets in PC lookup table")
118 table_assoc = Param.Int(4, "Associativity of PC lookup table")
119 use_master_id = Param.Bool(True, "Use master id based history")
120
121 degree = Param.Int(4, "Number of prefetches to generate")
122
123class TaggedPrefetcher(QueuedPrefetcher):
124 type = 'TaggedPrefetcher'
125 cxx_class = 'TaggedPrefetcher'
126 cxx_header = "mem/cache/prefetch/tagged.hh"
127
128 degree = Param.Int(2, "Number of prefetches to generate")
| 118 max_conf = Param.Int(7, "Maximum confidence level")
119 thresh_conf = Param.Int(4, "Threshold confidence level")
120 min_conf = Param.Int(0, "Minimum confidence level")
121 start_conf = Param.Int(4, "Starting confidence for new entries")
122
123 table_sets = Param.Int(16, "Number of sets in PC lookup table")
124 table_assoc = Param.Int(4, "Associativity of PC lookup table")
125 use_master_id = Param.Bool(True, "Use master id based history")
126
127 degree = Param.Int(4, "Number of prefetches to generate")
128
129class TaggedPrefetcher(QueuedPrefetcher):
130 type = 'TaggedPrefetcher'
131 cxx_class = 'TaggedPrefetcher'
132 cxx_header = "mem/cache/prefetch/tagged.hh"
133
134 degree = Param.Int(2, "Number of prefetches to generate")
|