1# Copyright (c) 2012 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated
10# unmodified and in its entirety in all distributions of the software,
11# modified or unmodified, in source code or in binary form.
12#
13# Copyright (c) 2005 The Regents of The University of Michigan
14# All rights reserved.
15#
16# Redistribution and use in source and binary forms, with or without
17# modification, are permitted provided that the following conditions are
18# met: redistributions of source code must retain the above copyright
19# notice, this list of conditions and the following disclaimer;
20# redistributions in binary form must reproduce the above copyright
21# notice, this list of conditions and the following disclaimer in the
22# documentation and/or other materials provided with the distribution;
23# neither the name of the copyright holders nor the names of its
24# contributors may be used to endorse or promote products derived from
25# this software without specific prior written permission.
26#
27# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
30# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
31# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
32# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
33# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
34# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
35# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
36# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
37# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38#
39# Authors: Ron Dreslinski
40
41from ClockedObject import ClockedObject
42from m5.params import *
43from m5.proxy import *
44
45class BasePrefetcher(ClockedObject):
46 type = 'BasePrefetcher'
47 abstract = True
48 cxx_header = "mem/cache/prefetch/base.hh"
49 size = Param.Int(100,
50 "Number of entries in the hardware prefetch queue")
51 cross_pages = Param.Bool(False,
52 "Allow prefetches to cross virtual page boundaries")
53 serial_squash = Param.Bool(False,
54 "Squash prefetches with a later time on a subsequent miss")
55 degree = Param.Int(1,
56 "Degree of the prefetch depth")
57 latency = Param.Cycles('1', "Latency of the prefetcher")
58 use_master_id = Param.Bool(True,
59 "Use the master id to separate calculations of prefetches")
60 data_accesses_only = Param.Bool(False,
61 "Only prefetch on data not on instruction accesses")
62 on_miss_only = Param.Bool(False,
63 "Only prefetch on miss (as opposed to always)")
64 on_read_only = Param.Bool(False,
65 "Only prefetch on read requests (write requests ignored)")
66 on_prefetch = Param.Bool(True,
67 "Let lower cache prefetcher train on prefetch requests")
| 1# Copyright (c) 2012 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated
10# unmodified and in its entirety in all distributions of the software,
11# modified or unmodified, in source code or in binary form.
12#
13# Copyright (c) 2005 The Regents of The University of Michigan
14# All rights reserved.
15#
16# Redistribution and use in source and binary forms, with or without
17# modification, are permitted provided that the following conditions are
18# met: redistributions of source code must retain the above copyright
19# notice, this list of conditions and the following disclaimer;
20# redistributions in binary form must reproduce the above copyright
21# notice, this list of conditions and the following disclaimer in the
22# documentation and/or other materials provided with the distribution;
23# neither the name of the copyright holders nor the names of its
24# contributors may be used to endorse or promote products derived from
25# this software without specific prior written permission.
26#
27# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
30# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
31# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
32# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
33# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
34# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
35# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
36# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
37# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38#
39# Authors: Ron Dreslinski
40
41from ClockedObject import ClockedObject
42from m5.params import *
43from m5.proxy import *
44
45class BasePrefetcher(ClockedObject):
46 type = 'BasePrefetcher'
47 abstract = True
48 cxx_header = "mem/cache/prefetch/base.hh"
49 size = Param.Int(100,
50 "Number of entries in the hardware prefetch queue")
51 cross_pages = Param.Bool(False,
52 "Allow prefetches to cross virtual page boundaries")
53 serial_squash = Param.Bool(False,
54 "Squash prefetches with a later time on a subsequent miss")
55 degree = Param.Int(1,
56 "Degree of the prefetch depth")
57 latency = Param.Cycles('1', "Latency of the prefetcher")
58 use_master_id = Param.Bool(True,
59 "Use the master id to separate calculations of prefetches")
60 data_accesses_only = Param.Bool(False,
61 "Only prefetch on data not on instruction accesses")
62 on_miss_only = Param.Bool(False,
63 "Only prefetch on miss (as opposed to always)")
64 on_read_only = Param.Bool(False,
65 "Only prefetch on read requests (write requests ignored)")
66 on_prefetch = Param.Bool(True,
67 "Let lower cache prefetcher train on prefetch requests")
|