1from m5.SimObject import SimObject
2from m5.params import *
3class BasePrefetcher(SimObject):
4 type = 'BasePrefetcher'
5 abstract = True
6 size = Param.Int(100,
7 "Number of entries in the hardware prefetch queue")
8 cross_pages = Param.Bool(False,
9 "Allow prefetches to cross virtual page boundaries")
10 serial_squash = Param.Bool(False,
11 "Squash prefetches with a later time on a subsequent miss")
12 degree = Param.Int(1,
13 "Degree of the prefetch depth")
14 latency = Param.Latency('10t',
15 "Latency of the prefetcher")
16 use_cpu_id = Param.Bool(True,
17 "Use the CPU ID to separate calculations of prefetches")
18 data_accesses_only = Param.Bool(False,
19 "Only prefetch on data not on instruction accesses")
20
21class GHBPrefetcher(BasePrefetcher):
22 type = 'GHBPrefetcher'
23 cxx_class = 'GHBPrefetcher'
24
25class StridePrefetcher(BasePrefetcher):
26 type = 'StridePrefetcher'
27 cxx_class = 'StridePrefetcher'
28
29class TaggedPrefetcher(BasePrefetcher):
30 type = 'TaggedPrefetcher'
31 cxx_class = 'TaggedPrefetcher'
32
33
34
35