noncoherent_cache.cc (13948:f8666d4d5855) noncoherent_cache.cc (14035:60068a2d56e0)
1/*
2 * Copyright (c) 2010-2018 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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75 // As this a non-coherent cache located below the point of
76 // coherency, we do not expect requests that are typically used to
77 // keep caches coherent (e.g., InvalidateReq or UpdateReq).
78 assert(pkt->isRead() || pkt->isWrite());
79 BaseCache::satisfyRequest(pkt, blk);
80}
81
82bool
1/*
2 * Copyright (c) 2010-2018 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 66 unchanged lines hidden (view full) ---

75 // As this a non-coherent cache located below the point of
76 // coherency, we do not expect requests that are typically used to
77 // keep caches coherent (e.g., InvalidateReq or UpdateReq).
78 assert(pkt->isRead() || pkt->isWrite());
79 BaseCache::satisfyRequest(pkt, blk);
80}
81
82bool
83NoncoherentCache::access(PacketPtr pkt, CacheBlk *&blk, Cycles &lat)
83NoncoherentCache::access(PacketPtr pkt, CacheBlk *&blk, Cycles &lat,
84 PacketList &writebacks)
84{
85{
85 bool success = BaseCache::access(pkt, blk, lat);
86 bool success = BaseCache::access(pkt, blk, lat, writebacks);
86
87 if (pkt->isWriteback() || pkt->cmd == MemCmd::WriteClean) {
88 assert(blk && blk->isValid());
89 // Writeback and WriteClean can allocate and fill even if the
90 // referenced block was not present or it was invalid. If that
91 // is the case, make sure that the new block is marked as
92 // writable
93 blk->status |= BlkWritable;
94 }
95
96 return success;
97}
98
99void
87
88 if (pkt->isWriteback() || pkt->cmd == MemCmd::WriteClean) {
89 assert(blk && blk->isValid());
90 // Writeback and WriteClean can allocate and fill even if the
91 // referenced block was not present or it was invalid. If that
92 // is the case, make sure that the new block is marked as
93 // writable
94 blk->status |= BlkWritable;
95 }
96
97 return success;
98}
99
100void
100NoncoherentCache::doWritebacks(PacketPtr pkt, Tick forward_time)
101NoncoherentCache::doWritebacks(PacketList& writebacks, Tick forward_time)
101{
102{
102 allocateWriteBuffer(pkt, forward_time);
103 while (!writebacks.empty()) {
104 PacketPtr wb_pkt = writebacks.front();
105 allocateWriteBuffer(wb_pkt, forward_time);
106 writebacks.pop_front();
107 }
103}
104
105void
108}
109
110void
106NoncoherentCache::doWritebacksAtomic(PacketPtr pkt)
111NoncoherentCache::doWritebacksAtomic(PacketList& writebacks)
107{
112{
108 memSidePort.sendAtomic(pkt);
109 delete pkt;
113 while (!writebacks.empty()) {
114 PacketPtr wb_pkt = writebacks.front();
115 memSidePort.sendAtomic(wb_pkt);
116 writebacks.pop_front();
117 delete wb_pkt;
118 }
110}
111
112void
113NoncoherentCache::handleTimingReqMiss(PacketPtr pkt, CacheBlk *blk,
114 Tick forward_time, Tick request_time)
115{
116 // miss
117 Addr blk_addr = pkt->getBlockAddr(blkSize);

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157 pkt->allocate();
158 DPRINTF(Cache, "%s created %s from %s\n", __func__, pkt->print(),
159 cpu_pkt->print());
160 return pkt;
161}
162
163
164Cycles
119}
120
121void
122NoncoherentCache::handleTimingReqMiss(PacketPtr pkt, CacheBlk *blk,
123 Tick forward_time, Tick request_time)
124{
125 // miss
126 Addr blk_addr = pkt->getBlockAddr(blkSize);

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166 pkt->allocate();
167 DPRINTF(Cache, "%s created %s from %s\n", __func__, pkt->print(),
168 cpu_pkt->print());
169 return pkt;
170}
171
172
173Cycles
165NoncoherentCache::handleAtomicReqMiss(PacketPtr pkt, CacheBlk *&blk)
174NoncoherentCache::handleAtomicReqMiss(PacketPtr pkt, CacheBlk *&blk,
175 PacketList &writebacks)
166{
167 PacketPtr bus_pkt = createMissPacket(pkt, blk, true,
168 pkt->isWholeLineWrite(blkSize));
169 DPRINTF(Cache, "Sending an atomic %s\n", bus_pkt->print());
170
171 Cycles latency = ticksToCycles(memSidePort.sendAtomic(bus_pkt));
172
173 assert(bus_pkt->isResponse());

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182 // We are now dealing with the response handling
183 DPRINTF(Cache, "Receive response: %s\n", bus_pkt->print());
184
185 if (!bus_pkt->isError()) {
186 // Any reponse that does not have an error should be filling,
187 // afterall it is a read response
188 DPRINTF(Cache, "Block for addr %#llx being updated in Cache\n",
189 bus_pkt->getAddr());
176{
177 PacketPtr bus_pkt = createMissPacket(pkt, blk, true,
178 pkt->isWholeLineWrite(blkSize));
179 DPRINTF(Cache, "Sending an atomic %s\n", bus_pkt->print());
180
181 Cycles latency = ticksToCycles(memSidePort.sendAtomic(bus_pkt));
182
183 assert(bus_pkt->isResponse());

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192 // We are now dealing with the response handling
193 DPRINTF(Cache, "Receive response: %s\n", bus_pkt->print());
194
195 if (!bus_pkt->isError()) {
196 // Any reponse that does not have an error should be filling,
197 // afterall it is a read response
198 DPRINTF(Cache, "Block for addr %#llx being updated in Cache\n",
199 bus_pkt->getAddr());
190 blk = handleFill(bus_pkt, blk, allocOnFill(bus_pkt->cmd));
200 blk = handleFill(bus_pkt, blk, writebacks, allocOnFill(bus_pkt->cmd));
191 assert(blk);
192 }
193 satisfyRequest(pkt, blk);
194
195 maintainClusivity(true, blk);
196
197 // Use the separate bus_pkt to generate response to pkt and
198 // then delete it.

--- 158 unchanged lines hidden --- 		201 assert(blk);
202 }
203 satisfyRequest(pkt, blk);
204
205 maintainClusivity(true, blk);
206
207 // Use the separate bus_pkt to generate response to pkt and
208 // then delete it.

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