noncoherent_cache.cc (13859:4156ac0c7257) | noncoherent_cache.cc (13948:f8666d4d5855) |
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1/* 2 * Copyright (c) 2010-2018 ARM Limited 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 66 unchanged lines hidden (view full) --- 75 // As this a non-coherent cache located below the point of 76 // coherency, we do not expect requests that are typically used to 77 // keep caches coherent (e.g., InvalidateReq or UpdateReq). 78 assert(pkt->isRead() || pkt->isWrite()); 79 BaseCache::satisfyRequest(pkt, blk); 80} 81 82bool | 1/* 2 * Copyright (c) 2010-2018 ARM Limited 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 66 unchanged lines hidden (view full) --- 75 // As this a non-coherent cache located below the point of 76 // coherency, we do not expect requests that are typically used to 77 // keep caches coherent (e.g., InvalidateReq or UpdateReq). 78 assert(pkt->isRead() || pkt->isWrite()); 79 BaseCache::satisfyRequest(pkt, blk); 80} 81 82bool |
83NoncoherentCache::access(PacketPtr pkt, CacheBlk *&blk, Cycles &lat, 84 PacketList &writebacks) | 83NoncoherentCache::access(PacketPtr pkt, CacheBlk *&blk, Cycles &lat) |
85{ | 84{ |
86 bool success = BaseCache::access(pkt, blk, lat, writebacks); | 85 bool success = BaseCache::access(pkt, blk, lat); |
87 88 if (pkt->isWriteback() || pkt->cmd == MemCmd::WriteClean) { 89 assert(blk && blk->isValid()); 90 // Writeback and WriteClean can allocate and fill even if the 91 // referenced block was not present or it was invalid. If that 92 // is the case, make sure that the new block is marked as 93 // writable 94 blk->status |= BlkWritable; 95 } 96 97 return success; 98} 99 100void | 86 87 if (pkt->isWriteback() || pkt->cmd == MemCmd::WriteClean) { 88 assert(blk && blk->isValid()); 89 // Writeback and WriteClean can allocate and fill even if the 90 // referenced block was not present or it was invalid. If that 91 // is the case, make sure that the new block is marked as 92 // writable 93 blk->status |= BlkWritable; 94 } 95 96 return success; 97} 98 99void |
101NoncoherentCache::doWritebacks(PacketList& writebacks, Tick forward_time) | 100NoncoherentCache::doWritebacks(PacketPtr pkt, Tick forward_time) |
102{ | 101{ |
103 while (!writebacks.empty()) { 104 PacketPtr wb_pkt = writebacks.front(); 105 allocateWriteBuffer(wb_pkt, forward_time); 106 writebacks.pop_front(); 107 } | 102 allocateWriteBuffer(pkt, forward_time); |
108} 109 110void | 103} 104 105void |
111NoncoherentCache::doWritebacksAtomic(PacketList& writebacks) | 106NoncoherentCache::doWritebacksAtomic(PacketPtr pkt) |
112{ | 107{ |
113 while (!writebacks.empty()) { 114 PacketPtr wb_pkt = writebacks.front(); 115 memSidePort.sendAtomic(wb_pkt); 116 writebacks.pop_front(); 117 delete wb_pkt; 118 } | 108 memSidePort.sendAtomic(pkt); 109 delete pkt; |
119} 120 121void 122NoncoherentCache::handleTimingReqMiss(PacketPtr pkt, CacheBlk *blk, 123 Tick forward_time, Tick request_time) 124{ 125 // miss 126 Addr blk_addr = pkt->getBlockAddr(blkSize); --- 39 unchanged lines hidden (view full) --- 166 pkt->allocate(); 167 DPRINTF(Cache, "%s created %s from %s\n", __func__, pkt->print(), 168 cpu_pkt->print()); 169 return pkt; 170} 171 172 173Cycles | 110} 111 112void 113NoncoherentCache::handleTimingReqMiss(PacketPtr pkt, CacheBlk *blk, 114 Tick forward_time, Tick request_time) 115{ 116 // miss 117 Addr blk_addr = pkt->getBlockAddr(blkSize); --- 39 unchanged lines hidden (view full) --- 157 pkt->allocate(); 158 DPRINTF(Cache, "%s created %s from %s\n", __func__, pkt->print(), 159 cpu_pkt->print()); 160 return pkt; 161} 162 163 164Cycles |
174NoncoherentCache::handleAtomicReqMiss(PacketPtr pkt, CacheBlk *&blk, 175 PacketList &writebacks) | 165NoncoherentCache::handleAtomicReqMiss(PacketPtr pkt, CacheBlk *&blk) |
176{ 177 PacketPtr bus_pkt = createMissPacket(pkt, blk, true, 178 pkt->isWholeLineWrite(blkSize)); 179 DPRINTF(Cache, "Sending an atomic %s\n", bus_pkt->print()); 180 181 Cycles latency = ticksToCycles(memSidePort.sendAtomic(bus_pkt)); 182 183 assert(bus_pkt->isResponse()); --- 8 unchanged lines hidden (view full) --- 192 // We are now dealing with the response handling 193 DPRINTF(Cache, "Receive response: %s\n", bus_pkt->print()); 194 195 if (!bus_pkt->isError()) { 196 // Any reponse that does not have an error should be filling, 197 // afterall it is a read response 198 DPRINTF(Cache, "Block for addr %#llx being updated in Cache\n", 199 bus_pkt->getAddr()); | 166{ 167 PacketPtr bus_pkt = createMissPacket(pkt, blk, true, 168 pkt->isWholeLineWrite(blkSize)); 169 DPRINTF(Cache, "Sending an atomic %s\n", bus_pkt->print()); 170 171 Cycles latency = ticksToCycles(memSidePort.sendAtomic(bus_pkt)); 172 173 assert(bus_pkt->isResponse()); --- 8 unchanged lines hidden (view full) --- 182 // We are now dealing with the response handling 183 DPRINTF(Cache, "Receive response: %s\n", bus_pkt->print()); 184 185 if (!bus_pkt->isError()) { 186 // Any reponse that does not have an error should be filling, 187 // afterall it is a read response 188 DPRINTF(Cache, "Block for addr %#llx being updated in Cache\n", 189 bus_pkt->getAddr()); |
200 blk = handleFill(bus_pkt, blk, writebacks, allocOnFill(bus_pkt->cmd)); | 190 blk = handleFill(bus_pkt, blk, allocOnFill(bus_pkt->cmd)); |
201 assert(blk); 202 } 203 satisfyRequest(pkt, blk); 204 205 maintainClusivity(true, blk); 206 207 // Use the separate bus_pkt to generate response to pkt and 208 // then delete it. --- 158 unchanged lines hidden --- | 191 assert(blk); 192 } 193 satisfyRequest(pkt, blk); 194 195 maintainClusivity(true, blk); 196 197 // Use the separate bus_pkt to generate response to pkt and 198 // then delete it. --- 158 unchanged lines hidden --- |