noncoherent_cache.cc (13564:9bbd53a77887) noncoherent_cache.cc (13859:4156ac0c7257)
1/*
2 * Copyright (c) 2010-2018 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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240
241 BaseCache::functionalAccess(pkt, from_cpu_side);
242}
243
244void
245NoncoherentCache::serviceMSHRTargets(MSHR *mshr, const PacketPtr pkt,
246 CacheBlk *blk)
247{
1/*
2 * Copyright (c) 2010-2018 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 231 unchanged lines hidden (view full) ---

240
241 BaseCache::functionalAccess(pkt, from_cpu_side);
242}
243
244void
245NoncoherentCache::serviceMSHRTargets(MSHR *mshr, const PacketPtr pkt,
246 CacheBlk *blk)
247{
248 MSHR::Target *initial_tgt = mshr->getTarget();
249 // First offset for critical word first calculations
248 // First offset for critical word first calculations
250 const int initial_offset = initial_tgt->pkt->getOffset(blkSize);
249 const int initial_offset = mshr->getTarget()->pkt->getOffset(blkSize);
251
252 MSHR::TargetList targets = mshr->extractServiceableTargets(pkt);
253 for (auto &target: targets) {
254 Packet *tgt_pkt = target.pkt;
255
256 switch (target.source) {
257 case MSHR::Target::FromCPU:
258 // handle deferred requests comming from a cache or core

--- 109 unchanged lines hidden --- 		250
251 MSHR::TargetList targets = mshr->extractServiceableTargets(pkt);
252 for (auto &target: targets) {
253 Packet *tgt_pkt = target.pkt;
254
255 switch (target.source) {
256 case MSHR::Target::FromCPU:
257 // handle deferred requests comming from a cache or core

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