noncoherent_cache.cc (12749:223c83ed9979) noncoherent_cache.cc (13017:a620da03ab10)
1/*
2 * Copyright (c) 2010-2018 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 156 unchanged lines hidden (view full) ---

165 pkt->allocate();
166 DPRINTF(Cache, "%s created %s from %s\n", __func__, pkt->print(),
167 cpu_pkt->print());
168 return pkt;
169}
170
171
172Cycles
1/*
2 * Copyright (c) 2010-2018 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 156 unchanged lines hidden (view full) ---

165 pkt->allocate();
166 DPRINTF(Cache, "%s created %s from %s\n", __func__, pkt->print(),
167 cpu_pkt->print());
168 return pkt;
169}
170
171
172Cycles
173NoncoherentCache::handleAtomicReqMiss(PacketPtr pkt, CacheBlk *blk,
173NoncoherentCache::handleAtomicReqMiss(PacketPtr pkt, CacheBlk *&blk,
174 PacketList &writebacks)
175{
176 PacketPtr bus_pkt = createMissPacket(pkt, blk, true);
177 DPRINTF(Cache, "Sending an atomic %s\n", bus_pkt->print());
178
179 Cycles latency = ticksToCycles(memSidePort.sendAtomic(bus_pkt));
180
181 assert(bus_pkt->isResponse());

--- 193 unchanged lines hidden --- 		174 PacketList &writebacks)
175{
176 PacketPtr bus_pkt = createMissPacket(pkt, blk, true);
177 DPRINTF(Cache, "Sending an atomic %s\n", bus_pkt->print());
178
179 Cycles latency = ticksToCycles(memSidePort.sendAtomic(bus_pkt));
180
181 assert(bus_pkt->isResponse());

--- 193 unchanged lines hidden ---