1/* 2 * Copyright (c) 2010-2018 ARM Limited 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 134 unchanged lines hidden (view full) --- 143 panic_if(!(pkt->isRead() || pkt->isWrite()), 144 "Should only see read and writes at non-coherent cache\n"); 145 146 BaseCache::recvTimingReq(pkt); 147} 148 149PacketPtr 150NoncoherentCache::createMissPacket(PacketPtr cpu_pkt, CacheBlk *blk, |
151 bool needs_writable, 152 bool is_whole_line_write) const |
153{ 154 // We also fill for writebacks from the coherent caches above us, 155 // and they do not need responses 156 assert(cpu_pkt->needsResponse()); 157 158 // A miss can happen only due to missing block 159 assert(!blk || !blk->isValid()); 160 --- 8 unchanged lines hidden (view full) --- 169 return pkt; 170} 171 172 173Cycles 174NoncoherentCache::handleAtomicReqMiss(PacketPtr pkt, CacheBlk *&blk, 175 PacketList &writebacks) 176{ |
177 PacketPtr bus_pkt = createMissPacket(pkt, blk, true, 178 pkt->isWholeLineWrite(blkSize)); |
179 DPRINTF(Cache, "Sending an atomic %s\n", bus_pkt->print()); 180 181 Cycles latency = ticksToCycles(memSidePort.sendAtomic(bus_pkt)); 182 183 assert(bus_pkt->isResponse()); 184 // At the moment the only supported downstream requests we issue 185 // are ReadReq and therefore here we should only see the 186 // corresponding responses --- 190 unchanged lines hidden --- |