1/*
2 * Copyright (c) 2012-2013, 2015-2016 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2003-2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Erik Hallnor
41 * Andreas Sandberg
42 */
43
44/** @file
45 * Declaration of a structure to manage MSHRs.
46 */
47
48#ifndef __MEM_CACHE_MSHR_QUEUE_HH__
49#define __MEM_CACHE_MSHR_QUEUE_HH__
50
51#include <vector>
52
53#include "mem/cache/mshr.hh"
54#include "mem/cache/queue.hh"
55
56/**
57 * A Class for maintaining a list of pending and allocated memory requests.
58 */
59class MSHRQueue : public Queue<MSHR>
60{
61 private:
62
63 /**
64 * The number of entries to reserve for future demand accesses.
65 * Prevent prefetcher from taking all mshr entries
66 */
67 const int demandReserve;
68
69 public:
70
71 /**
72 * Create a queue with a given number of entries.
73 * @param num_entrys The number of entries in this queue.
74 * @param reserve The minimum number of entries needed to satisfy
75 * any access.
76 * @param demand_reserve The minimum number of entries needed to satisfy
77 * demand accesses.
78 */
79 MSHRQueue(const std::string &_label, int num_entries, int reserve,
80 int demand_reserve);
81
82 /**
83 * Allocates a new MSHR for the request and size. This places the request
84 * as the first target in the MSHR.
85 *
86 * @param blk_addr The address of the block.
87 * @param blk_size The number of bytes to request.
88 * @param pkt The original miss.
89 * @param when_ready When should the MSHR be ready to act upon.
90 * @param order The logical order of this MSHR
91 * @param alloc_on_fill Should the cache allocate a block on fill
92 *
93 * @return The a pointer to the MSHR allocated.
94 *
95 * @pre There are free entries.
96 */
97 MSHR *allocate(Addr blk_addr, unsigned blk_size, PacketPtr pkt,
98 Tick when_ready, Counter order, bool alloc_on_fill);
99
100 /**
101 * Moves the MSHR to the front of the pending list if it is not
102 * in service.
103 * @param mshr The entry to move.
104 */
105 void moveToFront(MSHR *mshr);
106
107 /**
108 * Mark the given MSHR as in service. This removes the MSHR from the
109 * readyList or deallocates the MSHR if it does not expect a response.
110 *
111 * @param mshr The MSHR to mark in service.
112 * @param pending_modified_resp Whether we expect a modified response
113 * from another cache
114 */
115 void markInService(MSHR *mshr, bool pending_modified_resp);
116
117 /**
118 * Mark an in service entry as pending, used to resend a request.
119 * @param mshr The MSHR to resend.
120 */
121 void markPending(MSHR *mshr);
122
123 /**
124 * Deallocate top target, possibly freeing the MSHR
125 * @return if MSHR queue is no longer full
126 */
127 bool forceDeallocateTarget(MSHR *mshr);
128
129 /**
130 * Returns true if the pending list is not empty.
131 * @return True if there are outstanding requests.
132 */
133 bool havePending() const
134 {
135 return !readyList.empty();
136 }
137
138 /**
139 * Returns true if sufficient mshrs for prefetch.
140 * @return True if sufficient mshrs for prefetch.
141 */
142 bool canPrefetch() const
143 {
144 // @todo we may want to revisit the +1, currently added to
145 // keep regressions unchanged
146 return (allocated < numEntries - (numReserve + 1 + demandReserve));
147 }
148};
149
150#endif //__MEM_CACHE_MSHR_QUEUE_HH__