1/* 2 * Copyright (c) 2012-2013, 2015 ARM Limited 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 55 unchanged lines hidden (view full) --- 64 freeList.push_back(®isters[i]); 65 } 66} 67 68MSHR * 69MSHRQueue::findMatch(Addr blk_addr, bool is_secure) const 70{ 71 for (const auto& mshr : allocatedList) { |
72 // we ignore any MSHRs allocated for uncacheable accesses and 73 // simply ignore them when matching, in the cache we never 74 // check for matches when adding new uncacheable entries, and 75 // we do not want normal cacheable accesses being added to an 76 // MSHR serving an uncacheable access 77 if (!mshr->isUncacheable() && mshr->blkAddr == blk_addr && 78 mshr->isSecure == is_secure) { |
79 return mshr; 80 } 81 } 82 return NULL; 83} 84 85bool 86MSHRQueue::findMatches(Addr blk_addr, bool is_secure, 87 vector<MSHR*>& matches) const 88{ 89 // Need an empty vector 90 assert(matches.empty()); 91 bool retval = false; 92 for (const auto& mshr : allocatedList) { |
93 if (!mshr->isUncacheable() && mshr->blkAddr == blk_addr && 94 mshr->isSecure == is_secure) { |
95 retval = true; 96 matches.push_back(mshr); 97 } 98 } 99 return retval; 100} 101 102 --- 177 unchanged lines hidden --- |