mshr.hh (12823:ba630bc7a36d) mshr.hh (13349:20890038e8a0)
1/*
2 * Copyright (c) 2012-2013, 2015-2016, 2018 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Erik Hallnor
1/*
2 * Copyright (c) 2012-2013, 2015-2016, 2018 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Erik Hallnor
41 * Nikos Nikoleris
41 */
42
43/**
44 * @file
45 * Miss Status and Handling Register (MSHR) declaration.
46 */
47
48#ifndef __MEM_CACHE_MSHR_HH__
49#define __MEM_CACHE_MSHR_HH__
50
51#include <cassert>
52#include <iosfwd>
53#include <list>
54#include <string>
42 */
43
44/**
45 * @file
46 * Miss Status and Handling Register (MSHR) declaration.
47 */
48
49#ifndef __MEM_CACHE_MSHR_HH__
50#define __MEM_CACHE_MSHR_HH__
51
52#include <cassert>
53#include <iosfwd>
54#include <list>
55#include <string>
56#include <vector>
55
56#include "base/printable.hh"
57#include "base/types.hh"
58#include "mem/cache/queue_entry.hh"
59#include "mem/packet.hh"
57
58#include "base/printable.hh"
59#include "base/types.hh"
60#include "mem/cache/queue_entry.hh"
61#include "mem/packet.hh"
62#include "mem/request.hh"
60#include "sim/core.hh"
61
62class BaseCache;
63
64/**
65 * Miss Status and handling Register. This class keeps all the information
66 * needed to handle a cache miss including a list of target requests.
67 * @sa \ref gem5MemorySystem "gem5 Memory System"

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110 /** Did we snoop an invalidate while waiting for data? */
111 bool postInvalidate;
112
113 /** Did we snoop a read while waiting for data? */
114 bool postDowngrade;
115
116 public:
117
63#include "sim/core.hh"
64
65class BaseCache;
66
67/**
68 * Miss Status and handling Register. This class keeps all the information
69 * needed to handle a cache miss including a list of target requests.
70 * @sa \ref gem5MemorySystem "gem5 Memory System"

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113 /** Did we snoop an invalidate while waiting for data? */
114 bool postInvalidate;
115
116 /** Did we snoop a read while waiting for data? */
117 bool postDowngrade;
118
119 public:
120
121 /** Track if we sent this as a whole line write or not */
122 bool wasWholeLineWrite;
123
118 /** True if the entry is just a simple forward from an upper level */
119 bool isForward;
120
121 class Target {
122 public:
123
124 enum Source {
125 FromCPU,

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182 *
183 * @param pkt Packet considered for the flag update
184 * @param source Indicates the source of the packet
185 * @param alloc_on_fill Whether the pkt would allocate on a fill
186 */
187 void updateFlags(PacketPtr pkt, Target::Source source,
188 bool alloc_on_fill);
189
124 /** True if the entry is just a simple forward from an upper level */
125 bool isForward;
126
127 class Target {
128 public:
129
130 enum Source {
131 FromCPU,

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188 *
189 * @param pkt Packet considered for the flag update
190 * @param source Indicates the source of the packet
191 * @param alloc_on_fill Whether the pkt would allocate on a fill
192 */
193 void updateFlags(PacketPtr pkt, Target::Source source,
194 bool alloc_on_fill);
195
196 /**
197 * Reset state
198 *
199 * @param blk_addr Address of the cache block
200 * @param blk_size Size of the cache block
201 */
202 void init(Addr blk_addr, Addr blk_size) {
203 blkAddr = blk_addr;
204 blkSize = blk_size;
205 writesBitmap.resize(blk_size);
206
207 resetFlags();
208 }
209
190 void resetFlags() {
210 void resetFlags() {
211 onlyWrites = true;
212 std::fill(writesBitmap.begin(), writesBitmap.end(), false);
213
191 needsWritable = false;
192 hasUpgrade = false;
193 allocOnFill = false;
194 hasFromCache = false;
195 }
196
197 /**
198 * Goes through the list of targets and uses them to populate
199 * the flags of this TargetList. When the function returns the
200 * flags are consistent with the properties of packets in the
201 * list.
202 */
203 void populateFlags();
204
205 /**
214 needsWritable = false;
215 hasUpgrade = false;
216 allocOnFill = false;
217 hasFromCache = false;
218 }
219
220 /**
221 * Goes through the list of targets and uses them to populate
222 * the flags of this TargetList. When the function returns the
223 * flags are consistent with the properties of packets in the
224 * list.
225 */
226 void populateFlags();
227
228 /**
229 * Add the specified packet in the TargetList. This function
230 * stores information related to the added packet and updates
231 * accordingly the flags.
232 *
233 * @param pkt Packet considered for adding
234 */
235 void updateWriteFlags(PacketPtr pkt) {
236 const Request::FlagsType noMergeFlags =
237 Request::UNCACHEABLE |
238 Request::STRICT_ORDER | Request::MMAPPED_IPR |
239 Request::PRIVILEGED | Request::LLSC |
240 Request::MEM_SWAP | Request::MEM_SWAP_COND |
241 Request::SECURE;
242
243 // if we have already seen writes for the full block stop
244 // here, this might be a full line write followed by
245 // other compatible requests (e.g., reads)
246 if (!isWholeLineWrite()) {
247 bool can_merge_write = pkt->isWrite() &&
248 ((pkt->req->getFlags() & noMergeFlags) == 0);
249 onlyWrites &= can_merge_write;
250 if (onlyWrites) {
251 auto offset = pkt->getOffset(blkSize);
252 auto begin = writesBitmap.begin() + offset;
253 std::fill(begin, begin + pkt->getSize(), true);
254 }
255 }
256 }
257
258 /**
206 * Tests if the flags of this TargetList have their default
207 * values.
259 * Tests if the flags of this TargetList have their default
260 * values.
261 *
262 * @return True if the TargetList are reset, false otherwise.
208 */
209 bool isReset() const {
210 return !needsWritable && !hasUpgrade && !allocOnFill &&
263 */
264 bool isReset() const {
265 return !needsWritable && !hasUpgrade && !allocOnFill &&
211 !hasFromCache;
266 !hasFromCache && onlyWrites;
212 }
213
214 /**
215 * Add the specified packet in the TargetList. This function
216 * stores information related to the added packet and updates
217 * accordingly the flags.
218 *
219 * @param pkt Packet considered for adding
220 * @param readTime Tick at which the packet is processed by this cache
221 * @param order A counter giving a unique id to each target
222 * @param source Indicates the source agent of the packet
223 * @param markPending Set for deferred targets or pending MSHRs
224 * @param alloc_on_fill Whether it should allocate on a fill
225 */
226 void add(PacketPtr pkt, Tick readyTime, Counter order,
267 }
268
269 /**
270 * Add the specified packet in the TargetList. This function
271 * stores information related to the added packet and updates
272 * accordingly the flags.
273 *
274 * @param pkt Packet considered for adding
275 * @param readTime Tick at which the packet is processed by this cache
276 * @param order A counter giving a unique id to each target
277 * @param source Indicates the source agent of the packet
278 * @param markPending Set for deferred targets or pending MSHRs
279 * @param alloc_on_fill Whether it should allocate on a fill
280 */
281 void add(PacketPtr pkt, Tick readyTime, Counter order,
227 Target::Source source, bool markPending,
228 bool alloc_on_fill);
282 Target::Source source, bool markPending, bool alloc_on_fill);
229
230 /**
231 * Convert upgrades to the equivalent request if the cache line they
232 * refer to would have been invalid (Upgrade -> ReadEx, SC* -> Fail).
233 * Used to rejig ordering between targets waiting on an MSHR. */
234 void replaceUpgrades();
235
236 void clearDownstreamPending();
237 void clearDownstreamPending(iterator begin, iterator end);
238 bool trySatisfyFunctional(PacketPtr pkt);
239 void print(std::ostream &os, int verbosity,
240 const std::string &prefix) const;
283
284 /**
285 * Convert upgrades to the equivalent request if the cache line they
286 * refer to would have been invalid (Upgrade -> ReadEx, SC* -> Fail).
287 * Used to rejig ordering between targets waiting on an MSHR. */
288 void replaceUpgrades();
289
290 void clearDownstreamPending();
291 void clearDownstreamPending(iterator begin, iterator end);
292 bool trySatisfyFunctional(PacketPtr pkt);
293 void print(std::ostream &os, int verbosity,
294 const std::string &prefix) const;
295
296 /**
297 * Check if this list contains only compatible writes, and if they
298 * span the entire cache line. This is used as part of the
299 * miss-packet creation. Note that new requests may arrive after a
300 * miss-packet has been created, and for the fill we therefore use
301 * the wasWholeLineWrite field.
302 */
303 bool isWholeLineWrite() const
304 {
305 return onlyWrites &&
306 std::all_of(writesBitmap.begin(),
307 writesBitmap.end(), [](bool i) { return i; });
308 }
309
310 private:
311 /** Address of the cache block for this list of targets. */
312 Addr blkAddr;
313
314 /** Size of the cache block. */
315 Addr blkSize;
316
317 /** Are we only dealing with writes. */
318 bool onlyWrites;
319
320 // NOTE: std::vector<bool> might not meet satisfy the
321 // ForwardIterator requirement and therefore cannot be used
322 // for writesBitmap.
323 /**
324 * Track which bytes are written by requests in this target
325 * list.
326 */
327 std::vector<char> writesBitmap;
241 };
242
243 /** A list of MSHRs. */
244 typedef std::list<MSHR *> List;
245 /** MSHR list iterator. */
246 typedef List::iterator Iterator;
247
248 /** The pending* and post* flags are only valid if inService is

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310 Iterator allocIter;
311
312 /** List of all requests that match the address */
313 TargetList targets;
314
315 TargetList deferredTargets;
316
317 public:
328 };
329
330 /** A list of MSHRs. */
331 typedef std::list<MSHR *> List;
332 /** MSHR list iterator. */
333 typedef List::iterator Iterator;
334
335 /** The pending* and post* flags are only valid if inService is

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397 Iterator allocIter;
398
399 /** List of all requests that match the address */
400 TargetList targets;
401
402 TargetList deferredTargets;
403
404 public:
405 /**
406 * Check if this MSHR contains only compatible writes, and if they
407 * span the entire cache line. This is used as part of the
408 * miss-packet creation. Note that new requests may arrive after a
409 * miss-packet has been created, and for the fill we therefore use
410 * the wasWholeLineWrite field.
411 */
412 bool isWholeLineWrite() const {
413 return targets.isWholeLineWrite();
414 }
318
319 /**
320 * Allocate a miss to this MSHR.
321 * @param blk_addr The address of the block.
322 * @param blk_size The number of bytes to request.
323 * @param pkt The original miss.
324 * @param when_ready When should the MSHR be ready to act upon.
325 * @param _order The logical order of this MSHR

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416 /**
417 * Allocate a miss to this MSHR.
418 * @param blk_addr The address of the block.
419 * @param blk_size The number of bytes to request.
420 * @param pkt The original miss.
421 * @param when_ready When should the MSHR be ready to act upon.
422 * @param _order The logical order of this MSHR

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