mshr.hh (12724:4f6fac3191d2) mshr.hh (12727:56c23b54bcb1)
1/*
2 * Copyright (c) 2012-2013, 2015-2016, 2018 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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43/**
44 * @file
45 * Miss Status and Handling Register (MSHR) declaration.
46 */
47
48#ifndef __MEM_CACHE_MSHR_HH__
49#define __MEM_CACHE_MSHR_HH__
50
1/*
2 * Copyright (c) 2012-2013, 2015-2016, 2018 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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43/**
44 * @file
45 * Miss Status and Handling Register (MSHR) declaration.
46 */
47
48#ifndef __MEM_CACHE_MSHR_HH__
49#define __MEM_CACHE_MSHR_HH__
50
51#include <cassert>
52#include <iosfwd>
51#include <list>
53#include <list>
54#include <string>
52
53#include "base/printable.hh"
55
56#include "base/printable.hh"
57#include "base/types.hh"
54#include "mem/cache/queue_entry.hh"
58#include "mem/cache/queue_entry.hh"
59#include "mem/packet.hh"
60#include "sim/core.hh"
55
56class BaseCache;
57
58/**
59 * Miss Status and handling Register. This class keeps all the information
60 * needed to handle a cache miss including a list of target requests.
61 * @sa \ref gem5MemorySystem "gem5 Memory System"
62 */

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62class BaseCache;
63
64/**
65 * Miss Status and handling Register. This class keeps all the information
66 * needed to handle a cache miss including a list of target requests.
67 * @sa \ref gem5MemorySystem "gem5 Memory System"
68 */

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