1/*
2 * Copyright (c) 2012-2013 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2002-2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Erik Hallnor
41 */
42
43/**
44 * @file
45 * Miss Status and Handling Register (MSHR) declaration.
46 */
47
48#ifndef __MSHR_HH__
49#define __MSHR_HH__
50
51#include <list>
52
53#include "base/printable.hh"
54#include "mem/packet.hh"
55
56class CacheBlk;
57class MSHRQueue;
58
59/**
60 * Miss Status and handling Register. This class keeps all the information
61 * needed to handle a cache miss including a list of target requests.
62 * @sa \ref gem5MemorySystem "gem5 Memory System"
63 */
64class MSHR : public Packet::SenderState, public Printable
65{
66
67 /**
68 * Consider the MSHRQueue a friend to avoid making everything public
69 */
70 friend class MSHRQueue;
71
72 private:
73
74 /** Cycle when ready to issue */
75 Tick readyTime;
76
77 /** True if the request is uncacheable */
78 bool _isUncacheable;
79
80 /** Flag set by downstream caches */
81 bool downstreamPending;
82
83 /** Will we have a dirty copy after this request? */
84 bool pendingDirty;
85
86 /** Did we snoop an invalidate while waiting for data? */
87 bool postInvalidate;
88
89 /** Did we snoop a read while waiting for data? */
90 bool postDowngrade;
91
92 public:
93
94 class Target {
95 public:
96
97 enum Source {
98 FromCPU,
99 FromSnoop,
100 FromPrefetcher
101 };
102
103 Tick recvTime; //!< Time when request was received (for stats)
104 Tick readyTime; //!< Time when request is ready to be serviced
105 Counter order; //!< Global order (for memory consistency mgmt)
106 PacketPtr pkt; //!< Pending request packet.
107 Source source; //!< Did request come from cpu, memory, or prefetcher?
108 bool markedPending; //!< Did we mark upstream MSHR
109 //!< as downstreamPending?
110
111 Target(PacketPtr _pkt, Tick _readyTime, Counter _order,
112 Source _source, bool _markedPending)
113 : recvTime(curTick()), readyTime(_readyTime), order(_order),
114 pkt(_pkt), source(_source), markedPending(_markedPending)
115 {}
116 };
117
118 class TargetList : public std::list<Target> {
119 /** Target list iterator. */
120 typedef std::list<Target>::iterator Iterator;
121 typedef std::list<Target>::const_iterator ConstIterator;
122
123 public:
124 bool needsExclusive;
125 bool hasUpgrade;
126
127 TargetList();
128 void resetFlags() { needsExclusive = hasUpgrade = false; }
129 bool isReset() { return !needsExclusive && !hasUpgrade; }
130 void add(PacketPtr pkt, Tick readyTime, Counter order,
131 Target::Source source, bool markPending);
132 void replaceUpgrades();
133 void clearDownstreamPending();
134 bool checkFunctional(PacketPtr pkt);
135 void print(std::ostream &os, int verbosity,
136 const std::string &prefix) const;
137 };
138
139 /** A list of MSHRs. */
140 typedef std::list<MSHR *> List;
141 /** MSHR list iterator. */
142 typedef List::iterator Iterator;
143 /** MSHR list const_iterator. */
144 typedef List::const_iterator ConstIterator;
145
146 /** Pointer to queue containing this MSHR. */
147 MSHRQueue *queue;
148
149 /** Order number assigned by the miss queue. */
150 Counter order;
151
152 /** Address of the request. */
153 Addr addr;
154
155 /** Size of the request. */
156 int size;
157
158 /** True if the request targets the secure memory space. */
159 bool isSecure;
160
161 /** True if the request has been sent to the bus. */
162 bool inService;
163
164 /** True if the request is just a simple forward from an upper level */
165 bool isForward;
166
167 /** The pending* and post* flags are only valid if inService is
168 * true. Using the accessor functions lets us detect if these
169 * flags are accessed improperly.
170 */
171
172 /** True if we need to get an exclusive copy of the block. */
173 bool needsExclusive() const { return targets.needsExclusive; }
174
175 bool isPendingDirty() const {
176 assert(inService); return pendingDirty;
177 }
178
179 bool hasPostInvalidate() const {
180 assert(inService); return postInvalidate;
181 }
182
183 bool hasPostDowngrade() const {
184 assert(inService); return postDowngrade;
185 }
186
187 /** Thread number of the miss. */
188 ThreadID threadNum;
189
190 private:
191
192 /** Data buffer (if needed). Currently used only for pending
193 * upgrade handling. */
194 uint8_t *data;
195
196 /**
197 * Pointer to this MSHR on the ready list.
198 * @sa MissQueue, MSHRQueue::readyList
199 */
200 Iterator readyIter;
201
202 /**
203 * Pointer to this MSHR on the allocated list.
204 * @sa MissQueue, MSHRQueue::allocatedList
205 */
206 Iterator allocIter;
207
208 /** List of all requests that match the address */
209 TargetList targets;
210
211 TargetList deferredTargets;
212
213 public:
214
215 bool isUncacheable() const { return _isUncacheable; }
216
217 /**
218 * Allocate a miss to this MSHR.
219 * @param cmd The requesting command.
220 * @param addr The address of the miss.
221 * @param asid The address space id of the miss.
222 * @param size The number of bytes to request.
223 * @param pkt The original miss.
224 */
225 void allocate(Addr addr, int size, PacketPtr pkt,
226 Tick when, Counter _order);
227
| 1/*
2 * Copyright (c) 2012-2013 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2002-2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Erik Hallnor
41 */
42
43/**
44 * @file
45 * Miss Status and Handling Register (MSHR) declaration.
46 */
47
48#ifndef __MSHR_HH__
49#define __MSHR_HH__
50
51#include <list>
52
53#include "base/printable.hh"
54#include "mem/packet.hh"
55
56class CacheBlk;
57class MSHRQueue;
58
59/**
60 * Miss Status and handling Register. This class keeps all the information
61 * needed to handle a cache miss including a list of target requests.
62 * @sa \ref gem5MemorySystem "gem5 Memory System"
63 */
64class MSHR : public Packet::SenderState, public Printable
65{
66
67 /**
68 * Consider the MSHRQueue a friend to avoid making everything public
69 */
70 friend class MSHRQueue;
71
72 private:
73
74 /** Cycle when ready to issue */
75 Tick readyTime;
76
77 /** True if the request is uncacheable */
78 bool _isUncacheable;
79
80 /** Flag set by downstream caches */
81 bool downstreamPending;
82
83 /** Will we have a dirty copy after this request? */
84 bool pendingDirty;
85
86 /** Did we snoop an invalidate while waiting for data? */
87 bool postInvalidate;
88
89 /** Did we snoop a read while waiting for data? */
90 bool postDowngrade;
91
92 public:
93
94 class Target {
95 public:
96
97 enum Source {
98 FromCPU,
99 FromSnoop,
100 FromPrefetcher
101 };
102
103 Tick recvTime; //!< Time when request was received (for stats)
104 Tick readyTime; //!< Time when request is ready to be serviced
105 Counter order; //!< Global order (for memory consistency mgmt)
106 PacketPtr pkt; //!< Pending request packet.
107 Source source; //!< Did request come from cpu, memory, or prefetcher?
108 bool markedPending; //!< Did we mark upstream MSHR
109 //!< as downstreamPending?
110
111 Target(PacketPtr _pkt, Tick _readyTime, Counter _order,
112 Source _source, bool _markedPending)
113 : recvTime(curTick()), readyTime(_readyTime), order(_order),
114 pkt(_pkt), source(_source), markedPending(_markedPending)
115 {}
116 };
117
118 class TargetList : public std::list<Target> {
119 /** Target list iterator. */
120 typedef std::list<Target>::iterator Iterator;
121 typedef std::list<Target>::const_iterator ConstIterator;
122
123 public:
124 bool needsExclusive;
125 bool hasUpgrade;
126
127 TargetList();
128 void resetFlags() { needsExclusive = hasUpgrade = false; }
129 bool isReset() { return !needsExclusive && !hasUpgrade; }
130 void add(PacketPtr pkt, Tick readyTime, Counter order,
131 Target::Source source, bool markPending);
132 void replaceUpgrades();
133 void clearDownstreamPending();
134 bool checkFunctional(PacketPtr pkt);
135 void print(std::ostream &os, int verbosity,
136 const std::string &prefix) const;
137 };
138
139 /** A list of MSHRs. */
140 typedef std::list<MSHR *> List;
141 /** MSHR list iterator. */
142 typedef List::iterator Iterator;
143 /** MSHR list const_iterator. */
144 typedef List::const_iterator ConstIterator;
145
146 /** Pointer to queue containing this MSHR. */
147 MSHRQueue *queue;
148
149 /** Order number assigned by the miss queue. */
150 Counter order;
151
152 /** Address of the request. */
153 Addr addr;
154
155 /** Size of the request. */
156 int size;
157
158 /** True if the request targets the secure memory space. */
159 bool isSecure;
160
161 /** True if the request has been sent to the bus. */
162 bool inService;
163
164 /** True if the request is just a simple forward from an upper level */
165 bool isForward;
166
167 /** The pending* and post* flags are only valid if inService is
168 * true. Using the accessor functions lets us detect if these
169 * flags are accessed improperly.
170 */
171
172 /** True if we need to get an exclusive copy of the block. */
173 bool needsExclusive() const { return targets.needsExclusive; }
174
175 bool isPendingDirty() const {
176 assert(inService); return pendingDirty;
177 }
178
179 bool hasPostInvalidate() const {
180 assert(inService); return postInvalidate;
181 }
182
183 bool hasPostDowngrade() const {
184 assert(inService); return postDowngrade;
185 }
186
187 /** Thread number of the miss. */
188 ThreadID threadNum;
189
190 private:
191
192 /** Data buffer (if needed). Currently used only for pending
193 * upgrade handling. */
194 uint8_t *data;
195
196 /**
197 * Pointer to this MSHR on the ready list.
198 * @sa MissQueue, MSHRQueue::readyList
199 */
200 Iterator readyIter;
201
202 /**
203 * Pointer to this MSHR on the allocated list.
204 * @sa MissQueue, MSHRQueue::allocatedList
205 */
206 Iterator allocIter;
207
208 /** List of all requests that match the address */
209 TargetList targets;
210
211 TargetList deferredTargets;
212
213 public:
214
215 bool isUncacheable() const { return _isUncacheable; }
216
217 /**
218 * Allocate a miss to this MSHR.
219 * @param cmd The requesting command.
220 * @param addr The address of the miss.
221 * @param asid The address space id of the miss.
222 * @param size The number of bytes to request.
223 * @param pkt The original miss.
224 */
225 void allocate(Addr addr, int size, PacketPtr pkt,
226 Tick when, Counter _order);
227
|
229
230 void clearDownstreamPending();
231
232 /**
233 * Mark this MSHR as free.
234 */
235 void deallocate();
236
237 /**
238 * Add a request to the list of targets.
239 * @param target The target.
240 */
241 void allocateTarget(PacketPtr target, Tick when, Counter order);
242 bool handleSnoop(PacketPtr target, Counter order);
243
244 /** A simple constructor. */
245 MSHR();
246
247 /**
248 * Returns the current number of allocated targets.
249 * @return The current number of allocated targets.
250 */
251 int getNumTargets() const
252 { return targets.size() + deferredTargets.size(); }
253
254 /**
255 * Returns true if there are targets left.
256 * @return true if there are targets
257 */
258 bool hasTargets() const { return !targets.empty(); }
259
260 /**
261 * Returns a reference to the first target.
262 * @return A pointer to the first target.
263 */
264 Target *getTarget()
265 {
266 assert(hasTargets());
267 return &targets.front();
268 }
269
270 /**
271 * Pop first target.
272 */
273 void popTarget()
274 {
275 targets.pop_front();
276 }
277
278 bool isForwardNoResponse() const
279 {
280 if (getNumTargets() != 1)
281 return false;
282 const Target *tgt = &targets.front();
283 return tgt->source == Target::FromCPU && !tgt->pkt->needsResponse();
284 }
285
286 bool promoteDeferredTargets();
287
288 void handleFill(Packet *pkt, CacheBlk *blk);
289
290 bool checkFunctional(PacketPtr pkt);
291
292 /**
293 * Prints the contents of this MSHR for debugging.
294 */
295 void print(std::ostream &os,
296 int verbosity = 0,
297 const std::string &prefix = "") const;
298 /**
299 * A no-args wrapper of print(std::ostream...) meant to be
300 * invoked from DPRINTFs avoiding string overheads in fast mode
301 *
302 * @return string with mshr fields + [deferred]targets
303 */
304 std::string print() const;
305};
306
307#endif //__MSHR_HH__
| 229
230 void clearDownstreamPending();
231
232 /**
233 * Mark this MSHR as free.
234 */
235 void deallocate();
236
237 /**
238 * Add a request to the list of targets.
239 * @param target The target.
240 */
241 void allocateTarget(PacketPtr target, Tick when, Counter order);
242 bool handleSnoop(PacketPtr target, Counter order);
243
244 /** A simple constructor. */
245 MSHR();
246
247 /**
248 * Returns the current number of allocated targets.
249 * @return The current number of allocated targets.
250 */
251 int getNumTargets() const
252 { return targets.size() + deferredTargets.size(); }
253
254 /**
255 * Returns true if there are targets left.
256 * @return true if there are targets
257 */
258 bool hasTargets() const { return !targets.empty(); }
259
260 /**
261 * Returns a reference to the first target.
262 * @return A pointer to the first target.
263 */
264 Target *getTarget()
265 {
266 assert(hasTargets());
267 return &targets.front();
268 }
269
270 /**
271 * Pop first target.
272 */
273 void popTarget()
274 {
275 targets.pop_front();
276 }
277
278 bool isForwardNoResponse() const
279 {
280 if (getNumTargets() != 1)
281 return false;
282 const Target *tgt = &targets.front();
283 return tgt->source == Target::FromCPU && !tgt->pkt->needsResponse();
284 }
285
286 bool promoteDeferredTargets();
287
288 void handleFill(Packet *pkt, CacheBlk *blk);
289
290 bool checkFunctional(PacketPtr pkt);
291
292 /**
293 * Prints the contents of this MSHR for debugging.
294 */
295 void print(std::ostream &os,
296 int verbosity = 0,
297 const std::string &prefix = "") const;
298 /**
299 * A no-args wrapper of print(std::ostream...) meant to be
300 * invoked from DPRINTFs avoiding string overheads in fast mode
301 *
302 * @return string with mshr fields + [deferred]targets
303 */
304 std::string print() const;
305};
306
307#endif //__MSHR_HH__
|