1/*
2 * Copyright (c) 2012-2013, 2015-2016, 2018 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
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33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Erik Hallnor
41 */
42
43/**
44 * @file
45 * Miss Status and Handling Register (MSHR) declaration.
46 */
47
48#ifndef __MEM_CACHE_MSHR_HH__
49#define __MEM_CACHE_MSHR_HH__
50
51#include <cassert>
52#include <iosfwd>
53#include <list>
54#include <string>
55
56#include "base/printable.hh"
57#include "base/types.hh"
58#include "mem/cache/queue_entry.hh"
59#include "mem/packet.hh"
60#include "sim/core.hh"
61
62class BaseCache;
63
64/**
65 * Miss Status and handling Register. This class keeps all the information
66 * needed to handle a cache miss including a list of target requests.
67 * @sa \ref gem5MemorySystem "gem5 Memory System"
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110 /** Did we snoop an invalidate while waiting for data? */
111 bool postInvalidate;
112
113 /** Did we snoop a read while waiting for data? */
114 bool postDowngrade;
115
116 public:
117
118 /** True if the entry is just a simple forward from an upper level */
119 bool isForward;
120
121 class Target {
122 public:
123
124 enum Source {
125 FromCPU,
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182 *
183 * @param pkt Packet considered for the flag update
184 * @param source Indicates the source of the packet
185 * @param alloc_on_fill Whether the pkt would allocate on a fill
186 */
187 void updateFlags(PacketPtr pkt, Target::Source source,
188 bool alloc_on_fill);
189
190 void resetFlags() {
191 needsWritable = false;
192 hasUpgrade = false;
193 allocOnFill = false;
194 hasFromCache = false;
195 }
196
197 /**
198 * Goes through the list of targets and uses them to populate
199 * the flags of this TargetList. When the function returns the
200 * flags are consistent with the properties of packets in the
201 * list.
202 */
203 void populateFlags();
204
205 /**
206 * Tests if the flags of this TargetList have their default
207 * values.
208 */
209 bool isReset() const {
210 return !needsWritable && !hasUpgrade && !allocOnFill &&
211 !hasFromCache;
212 }
213
214 /**
215 * Add the specified packet in the TargetList. This function
216 * stores information related to the added packet and updates
217 * accordingly the flags.
218 *
219 * @param pkt Packet considered for adding
220 * @param readTime Tick at which the packet is processed by this cache
221 * @param order A counter giving a unique id to each target
222 * @param source Indicates the source agent of the packet
223 * @param markPending Set for deferred targets or pending MSHRs
224 * @param alloc_on_fill Whether it should allocate on a fill
225 */
226 void add(PacketPtr pkt, Tick readyTime, Counter order,
227 Target::Source source, bool markPending,
228 bool alloc_on_fill);
229
230 /**
231 * Convert upgrades to the equivalent request if the cache line they
232 * refer to would have been invalid (Upgrade -> ReadEx, SC* -> Fail).
233 * Used to rejig ordering between targets waiting on an MSHR. */
234 void replaceUpgrades();
235
236 void clearDownstreamPending();
237 void clearDownstreamPending(iterator begin, iterator end);
238 bool trySatisfyFunctional(PacketPtr pkt);
239 void print(std::ostream &os, int verbosity,
240 const std::string &prefix) const;
241 };
242
243 /** A list of MSHRs. */
244 typedef std::list<MSHR *> List;
245 /** MSHR list iterator. */
246 typedef List::iterator Iterator;
247
248 /** The pending* and post* flags are only valid if inService is
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310 Iterator allocIter;
311
312 /** List of all requests that match the address */
313 TargetList targets;
314
315 TargetList deferredTargets;
316
317 public:
318
319 /**
320 * Allocate a miss to this MSHR.
321 * @param blk_addr The address of the block.
322 * @param blk_size The number of bytes to request.
323 * @param pkt The original miss.
324 * @param when_ready When should the MSHR be ready to act upon.
325 * @param _order The logical order of this MSHR
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2 * Copyright (c) 2012-2013, 2015-2016, 2018 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
--- 24 unchanged lines hidden (view full) ---
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Erik Hallnor
41 */
42
43/**
44 * @file
45 * Miss Status and Handling Register (MSHR) declaration.
46 */
47
48#ifndef __MEM_CACHE_MSHR_HH__
49#define __MEM_CACHE_MSHR_HH__
50
51#include <cassert>
52#include <iosfwd>
53#include <list>
54#include <string>
55
56#include "base/printable.hh"
57#include "base/types.hh"
58#include "mem/cache/queue_entry.hh"
59#include "mem/packet.hh"
60#include "sim/core.hh"
61
62class BaseCache;
63
64/**
65 * Miss Status and handling Register. This class keeps all the information
66 * needed to handle a cache miss including a list of target requests.
67 * @sa \ref gem5MemorySystem "gem5 Memory System"
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110 /** Did we snoop an invalidate while waiting for data? */
111 bool postInvalidate;
112
113 /** Did we snoop a read while waiting for data? */
114 bool postDowngrade;
115
116 public:
117
118 /** True if the entry is just a simple forward from an upper level */
119 bool isForward;
120
121 class Target {
122 public:
123
124 enum Source {
125 FromCPU,
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182 *
183 * @param pkt Packet considered for the flag update
184 * @param source Indicates the source of the packet
185 * @param alloc_on_fill Whether the pkt would allocate on a fill
186 */
187 void updateFlags(PacketPtr pkt, Target::Source source,
188 bool alloc_on_fill);
189
190 void resetFlags() {
191 needsWritable = false;
192 hasUpgrade = false;
193 allocOnFill = false;
194 hasFromCache = false;
195 }
196
197 /**
198 * Goes through the list of targets and uses them to populate
199 * the flags of this TargetList. When the function returns the
200 * flags are consistent with the properties of packets in the
201 * list.
202 */
203 void populateFlags();
204
205 /**
206 * Tests if the flags of this TargetList have their default
207 * values.
208 */
209 bool isReset() const {
210 return !needsWritable && !hasUpgrade && !allocOnFill &&
211 !hasFromCache;
212 }
213
214 /**
215 * Add the specified packet in the TargetList. This function
216 * stores information related to the added packet and updates
217 * accordingly the flags.
218 *
219 * @param pkt Packet considered for adding
220 * @param readTime Tick at which the packet is processed by this cache
221 * @param order A counter giving a unique id to each target
222 * @param source Indicates the source agent of the packet
223 * @param markPending Set for deferred targets or pending MSHRs
224 * @param alloc_on_fill Whether it should allocate on a fill
225 */
226 void add(PacketPtr pkt, Tick readyTime, Counter order,
227 Target::Source source, bool markPending,
228 bool alloc_on_fill);
229
230 /**
231 * Convert upgrades to the equivalent request if the cache line they
232 * refer to would have been invalid (Upgrade -> ReadEx, SC* -> Fail).
233 * Used to rejig ordering between targets waiting on an MSHR. */
234 void replaceUpgrades();
235
236 void clearDownstreamPending();
237 void clearDownstreamPending(iterator begin, iterator end);
238 bool trySatisfyFunctional(PacketPtr pkt);
239 void print(std::ostream &os, int verbosity,
240 const std::string &prefix) const;
241 };
242
243 /** A list of MSHRs. */
244 typedef std::list<MSHR *> List;
245 /** MSHR list iterator. */
246 typedef List::iterator Iterator;
247
248 /** The pending* and post* flags are only valid if inService is
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310 Iterator allocIter;
311
312 /** List of all requests that match the address */
313 TargetList targets;
314
315 TargetList deferredTargets;
316
317 public:
318
319 /**
320 * Allocate a miss to this MSHR.
321 * @param blk_addr The address of the block.
322 * @param blk_size The number of bytes to request.
323 * @param pkt The original miss.
324 * @param when_ready When should the MSHR be ready to act upon.
325 * @param _order The logical order of this MSHR
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