1/*
2 * Copyright (c) 2012-2013, 2015-2016 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated

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46 */
47
48#ifndef __MEM_CACHE_MSHR_HH__
49#define __MEM_CACHE_MSHR_HH__
50
51#include <list>
52
53#include "base/printable.hh"
54#include "mem/cache/queue_entry.hh"
55
56class Cache;
57
58/**
59 * Miss Status and handling Register. This class keeps all the information
60 * needed to handle a cache miss including a list of target requests.
61 * @sa \ref gem5MemorySystem "gem5 Memory System"
62 */
63class MSHR : public QueueEntry, public Printable
64{
65
66 /**
67 * Consider the queues friends to avoid making everything public.
68 */
69 template<typename Entry>
70 friend class Queue;
71 friend class MSHRQueue;
72
73 private:
74
75 /** Flag set by downstream caches */
76 bool downstreamPending;
77
78 /**
79 * Here we use one flag to track both if:
80 *
81 * 1. We are going to become owner or not, i.e., we will get the
82 * block in an ownership state (Owned or Modified) with BlkDirty

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104 /** Did we snoop an invalidate while waiting for data? */
105 bool postInvalidate;
106
107 /** Did we snoop a read while waiting for data? */
108 bool postDowngrade;
109
110 public:
111
112 /** True if the entry is just a simple forward from an upper level */
113 bool isForward;
114
115 class Target {
116 public:
117
118 enum Source {
119 FromCPU,
120 FromSnoop,
121 FromPrefetcher
122 };

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159 void print(std::ostream &os, int verbosity,
160 const std::string &prefix) const;
161 };
162
163 /** A list of MSHRs. */
164 typedef std::list<MSHR *> List;
165 /** MSHR list iterator. */
166 typedef List::iterator Iterator;
167
168 /** Keep track of whether we should allocate on fill or not */
169 bool allocOnFill;
170
171 /** The pending* and post* flags are only valid if inService is
172 * true. Using the accessor functions lets us detect if these
173 * flags are accessed improperly.
174 */
175

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183 bool hasPostInvalidate() const {
184 assert(inService); return postInvalidate;
185 }
186
187 bool hasPostDowngrade() const {
188 assert(inService); return postDowngrade;
189 }
190
191 bool sendPacket(Cache &cache);
192
193 private:
194
195 /**
196 * Pointer to this MSHR on the ready list.
197 * @sa MissQueue, MSHRQueue::readyList
198 */
199 Iterator readyIter;
200
201 /**
202 * Pointer to this MSHR on the allocated list.
203 * @sa MissQueue, MSHRQueue::allocatedList
204 */
205 Iterator allocIter;
206
207 /** List of all requests that match the address */
208 TargetList targets;
209
210 TargetList deferredTargets;
211
212 public:
213
214 /**
215 * Allocate a miss to this MSHR.
216 * @param blk_addr The address of the block.
217 * @param blk_size The number of bytes to request.
218 * @param pkt The original miss.
219 * @param when_ready When should the MSHR be ready to act upon.
220 * @param _order The logical order of this MSHR
221 * @param alloc_on_fill Should the cache allocate a block on fill
222 */
223 void allocate(Addr blk_addr, unsigned blk_size, PacketPtr pkt,
224 Tick when_ready, Counter _order, bool alloc_on_fill);
225
226 void markInService(bool pending_modified_resp);
227
228 void clearDownstreamPending();
229
230 /**
231 * Mark this MSHR as free.
232 */
233 void deallocate();
234

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269 /**
270 * Pop first target.
271 */
272 void popTarget()
273 {
274 targets.pop_front();
275 }
276
277 bool promoteDeferredTargets();
278
279 void promoteWritable();
280
281 bool checkFunctional(PacketPtr pkt);
282
283 /**
284 * Prints the contents of this MSHR for debugging.

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