mshr.cc (12823:ba630bc7a36d) mshr.cc (13349:20890038e8a0)
1/*
2 * Copyright (c) 2012-2013, 2015-2018 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Erik Hallnor
42 * Dave Greene
1/*
2 * Copyright (c) 2012-2013, 2015-2018 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Erik Hallnor
42 * Dave Greene
43 * Nikos Nikoleris
43 */
44
45/**
46 * @file
47 * Miss Status and Handling Register (MSHR) definitions.
48 */
49
50#include "mem/cache/mshr.hh"

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58#include "debug/Cache.hh"
59#include "mem/cache/base.hh"
60#include "mem/request.hh"
61#include "sim/core.hh"
62
63MSHR::MSHR() : downstreamPending(false),
64 pendingModified(false),
65 postInvalidate(false), postDowngrade(false),
44 */
45
46/**
47 * @file
48 * Miss Status and Handling Register (MSHR) definitions.
49 */
50
51#include "mem/cache/mshr.hh"

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59#include "debug/Cache.hh"
60#include "mem/cache/base.hh"
61#include "mem/request.hh"
62#include "sim/core.hh"
63
64MSHR::MSHR() : downstreamPending(false),
65 pendingModified(false),
66 postInvalidate(false), postDowngrade(false),
66 isForward(false)
67 wasWholeLineWrite(false), isForward(false)
67{
68}
69
70MSHR::TargetList::TargetList()
71 : needsWritable(false), hasUpgrade(false), allocOnFill(false),
72 hasFromCache(false)
73{}
74

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90 }
91
92 // potentially re-evaluate whether we should allocate on a fill or
93 // not
94 allocOnFill = allocOnFill || alloc_on_fill;
95
96 if (source != Target::FromPrefetcher) {
97 hasFromCache = hasFromCache || pkt->fromCache();
68{
69}
70
71MSHR::TargetList::TargetList()
72 : needsWritable(false), hasUpgrade(false), allocOnFill(false),
73 hasFromCache(false)
74{}
75

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91 }
92
93 // potentially re-evaluate whether we should allocate on a fill or
94 // not
95 allocOnFill = allocOnFill || alloc_on_fill;
96
97 if (source != Target::FromPrefetcher) {
98 hasFromCache = hasFromCache || pkt->fromCache();
99
100 updateWriteFlags(pkt);
98 }
99 }
100}
101
102void
103MSHR::TargetList::populateFlags()
104{
105 resetFlags();

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252{
253 blkAddr = blk_addr;
254 blkSize = blk_size;
255 isSecure = target->isSecure();
256 readyTime = when_ready;
257 order = _order;
258 assert(target);
259 isForward = false;
101 }
102 }
103}
104
105void
106MSHR::TargetList::populateFlags()
107{
108 resetFlags();

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255{
256 blkAddr = blk_addr;
257 blkSize = blk_size;
258 isSecure = target->isSecure();
259 readyTime = when_ready;
260 order = _order;
261 assert(target);
262 isForward = false;
263 wasWholeLineWrite = false;
260 _isUncacheable = target->req->isUncacheable();
261 inService = false;
262 downstreamPending = false;
264 _isUncacheable = target->req->isUncacheable();
265 inService = false;
266 downstreamPending = false;
263 assert(targets.isReset());
267
268 targets.init(blkAddr, blkSize);
269 deferredTargets.init(blkAddr, blkSize);
270
264 // Don't know of a case where we would allocate a new MSHR for a
265 // snoop (mem-side request), so set source according to request here
266 Target::Source source = (target->cmd == MemCmd::HardPFReq) ?
267 Target::FromPrefetcher : Target::FromCPU;
268 targets.add(target, when_ready, _order, source, true, alloc_on_fill);
271 // Don't know of a case where we would allocate a new MSHR for a
272 // snoop (mem-side request), so set source according to request here
273 Target::Source source = (target->cmd == MemCmd::HardPFReq) ?
274 Target::FromPrefetcher : Target::FromCPU;
275 targets.add(target, when_ready, _order, source, true, alloc_on_fill);
269 assert(deferredTargets.isReset());
270}
271
272
273void
274MSHR::clearDownstreamPending()
275{
276 assert(downstreamPending);
277 downstreamPending = false;

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289 pendingModified = targets.needsWritable || pending_modified_resp;
290 postInvalidate = postDowngrade = false;
291
292 if (!downstreamPending) {
293 // let upstream caches know that the request has made it to a
294 // level where it's going to get a response
295 targets.clearDownstreamPending();
296 }
276}
277
278
279void
280MSHR::clearDownstreamPending()
281{
282 assert(downstreamPending);
283 downstreamPending = false;

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295 pendingModified = targets.needsWritable || pending_modified_resp;
296 postInvalidate = postDowngrade = false;
297
298 if (!downstreamPending) {
299 // let upstream caches know that the request has made it to a
300 // level where it's going to get a response
301 targets.clearDownstreamPending();
302 }
303 // if the line is not considered a whole-line write when sent
304 // downstream, make sure it is also not considered a whole-line
305 // write when receiving the response, and vice versa
306 wasWholeLineWrite = isWholeLineWrite();
297}
298
299
300void
301MSHR::deallocate()
302{
303 assert(targets.empty());
304 targets.resetFlags();

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475
476 return true;
477}
478
479MSHR::TargetList
480MSHR::extractServiceableTargets(PacketPtr pkt)
481{
482 TargetList ready_targets;
307}
308
309
310void
311MSHR::deallocate()
312{
313 assert(targets.empty());
314 targets.resetFlags();

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485
486 return true;
487}
488
489MSHR::TargetList
490MSHR::extractServiceableTargets(PacketPtr pkt)
491{
492 TargetList ready_targets;
493 ready_targets.init(blkAddr, blkSize);
483 // If the downstream MSHR got an invalidation request then we only
484 // service the first of the FromCPU targets and any other
485 // non-FromCPU target. This way the remaining FromCPU targets
486 // issue a new request and get a fresh copy of the block and we
487 // avoid memory consistency violations.
488 if (pkt->cmd == MemCmd::ReadRespWithInvalidate) {
489 auto it = targets.begin();
490 assert((it->source == Target::FromCPU) ||

--- 183 unchanged lines hidden --- 		494 // If the downstream MSHR got an invalidation request then we only
495 // service the first of the FromCPU targets and any other
496 // non-FromCPU target. This way the remaining FromCPU targets
497 // issue a new request and get a fresh copy of the block and we
498 // avoid memory consistency violations.
499 if (pkt->cmd == MemCmd::ReadRespWithInvalidate) {
500 auto it = targets.begin();
501 assert((it->source == Target::FromCPU) ||

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