1/*
2 * Copyright (c) 2012-2013, 2015 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2002-2005 The Regents of The University of Michigan
15 * Copyright (c) 2010 Advanced Micro Devices, Inc.
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Erik Hallnor
42 * Dave Greene
43 */
44
45/**
46 * @file
47 * Miss Status and Handling Register (MSHR) definitions.
48 */
49
50#include <algorithm>
51#include <cassert>
52#include <string>
53#include <vector>
54
55#include "base/misc.hh"
56#include "base/types.hh"
57#include "debug/Cache.hh"
58#include "mem/cache/cache.hh"
59#include "mem/cache/mshr.hh"
60#include "sim/core.hh"
61
62using namespace std;
63
64MSHR::MSHR() : readyTime(0), _isUncacheable(false), downstreamPending(false),
65 pendingDirty(false),
66 postInvalidate(false), postDowngrade(false),
67 queue(NULL), order(0), blkAddr(0),
68 blkSize(0), isSecure(false), inService(false),
69 isForward(false), threadNum(InvalidThreadID), data(NULL)
70{
71}
72
73
74MSHR::TargetList::TargetList()
75 : needsExclusive(false), hasUpgrade(false)
76{}
77
78
79inline void
80MSHR::TargetList::add(PacketPtr pkt, Tick readyTime,
81 Counter order, Target::Source source, bool markPending)
82{
83 if (source != Target::FromSnoop) {
84 if (pkt->needsExclusive()) {
85 needsExclusive = true;
86 }
87
88 // StoreCondReq is effectively an upgrade if it's in an MSHR
89 // since it would have been failed already if we didn't have a
90 // read-only copy
91 if (pkt->isUpgrade() || pkt->cmd == MemCmd::StoreCondReq) {
92 hasUpgrade = true;
93 }
94 }
95
96 if (markPending) {
97 // Iterate over the SenderState stack and see if we find
98 // an MSHR entry. If we do, set the downstreamPending
99 // flag. Otherwise, do nothing.
100 MSHR *mshr = pkt->findNextSenderState<MSHR>();
101 if (mshr != NULL) {
102 assert(!mshr->downstreamPending);
103 mshr->downstreamPending = true;
104 }
105 }
106
107 emplace_back(Target(pkt, readyTime, order, source, markPending));
108}
109
110
111static void
112replaceUpgrade(PacketPtr pkt)
113{
114 if (pkt->cmd == MemCmd::UpgradeReq) {
115 pkt->cmd = MemCmd::ReadExReq;
116 DPRINTF(Cache, "Replacing UpgradeReq with ReadExReq\n");
117 } else if (pkt->cmd == MemCmd::SCUpgradeReq) {
118 pkt->cmd = MemCmd::SCUpgradeFailReq;
119 DPRINTF(Cache, "Replacing SCUpgradeReq with SCUpgradeFailReq\n");
120 } else if (pkt->cmd == MemCmd::StoreCondReq) {
121 pkt->cmd = MemCmd::StoreCondFailReq;
122 DPRINTF(Cache, "Replacing StoreCondReq with StoreCondFailReq\n");
123 }
124}
125
126
127void
128MSHR::TargetList::replaceUpgrades()
129{
130 if (!hasUpgrade)
131 return;
132
133 for (auto& t : *this) {
134 replaceUpgrade(t.pkt);
135 }
136
137 hasUpgrade = false;
138}
139
140
141void
142MSHR::TargetList::clearDownstreamPending()
143{
144 for (auto& t : *this) {
145 if (t.markedPending) {
146 // Iterate over the SenderState stack and see if we find
147 // an MSHR entry. If we find one, clear the
148 // downstreamPending flag by calling
149 // clearDownstreamPending(). This recursively clears the
150 // downstreamPending flag in all caches this packet has
151 // passed through.
152 MSHR *mshr = t.pkt->findNextSenderState<MSHR>();
153 if (mshr != NULL) {
154 mshr->clearDownstreamPending();
155 }
156 }
157 }
158}
159
160
161bool
162MSHR::TargetList::checkFunctional(PacketPtr pkt)
163{
164 for (auto& t : *this) {
165 if (pkt->checkFunctional(t.pkt)) {
166 return true;
167 }
168 }
169
170 return false;
171}
172
173
174void
175MSHR::TargetList::print(std::ostream &os, int verbosity,
176 const std::string &prefix) const
177{
178 for (auto& t : *this) {
179 const char *s;
180 switch (t.source) {
181 case Target::FromCPU:
182 s = "FromCPU";
183 break;
184 case Target::FromSnoop:
185 s = "FromSnoop";
186 break;
187 case Target::FromPrefetcher:
188 s = "FromPrefetcher";
189 break;
190 default:
191 s = "";
192 break;
193 }
194 ccprintf(os, "%s%s: ", prefix, s);
195 t.pkt->print(os, verbosity, "");
196 }
197}
198
199
200void
201MSHR::allocate(Addr blk_addr, unsigned blk_size, PacketPtr target,
202 Tick when_ready, Counter _order)
203{
204 blkAddr = blk_addr;
205 blkSize = blk_size;
206 isSecure = target->isSecure();
207 readyTime = when_ready;
208 order = _order;
209 assert(target);
210 isForward = false;
211 _isUncacheable = target->req->isUncacheable();
212 inService = false;
213 downstreamPending = false;
214 threadNum = 0;
215 assert(targets.isReset());
216 // Don't know of a case where we would allocate a new MSHR for a
217 // snoop (mem-side request), so set source according to request here
218 Target::Source source = (target->cmd == MemCmd::HardPFReq) ?
219 Target::FromPrefetcher : Target::FromCPU;
220 targets.add(target, when_ready, _order, source, true);
221 assert(deferredTargets.isReset());
222 data = NULL;
223}
224
225
226void
227MSHR::clearDownstreamPending()
228{
229 assert(downstreamPending);
230 downstreamPending = false;
231 // recursively clear flag on any MSHRs we will be forwarding
232 // responses to
233 targets.clearDownstreamPending();
234}
235
236bool
237MSHR::markInService(bool pending_dirty_resp)
238{
239 assert(!inService);
240 if (isForwardNoResponse()) {
241 // we just forwarded the request packet & don't expect a
242 // response, so get rid of it
243 assert(getNumTargets() == 1);
244 popTarget();
245 return true;
246 }
247
248 inService = true;
249 pendingDirty = targets.needsExclusive || pending_dirty_resp;
250 postInvalidate = postDowngrade = false;
251
252 if (!downstreamPending) {
253 // let upstream caches know that the request has made it to a
254 // level where it's going to get a response
255 targets.clearDownstreamPending();
256 }
257 return false;
258}
259
260
261void
262MSHR::deallocate()
263{
264 assert(targets.empty());
265 targets.resetFlags();
266 assert(deferredTargets.isReset());
267 inService = false;
268}
269
270/*
271 * Adds a target to an MSHR
272 */
273void
274MSHR::allocateTarget(PacketPtr pkt, Tick whenReady, Counter _order)
275{
276 // assume we'd never issue a prefetch when we've got an
277 // outstanding miss
278 assert(pkt->cmd != MemCmd::HardPFReq);
279
280 // uncacheable accesses always allocate a new MSHR, and cacheable
281 // accesses ignore any uncacheable MSHRs, thus we should never
282 // have targets addded if originally allocated uncacheable
283 assert(!_isUncacheable);
284
285 // if there's a request already in service for this MSHR, we will
286 // have to defer the new target until after the response if any of
287 // the following are true:
288 // - there are other targets already deferred
289 // - there's a pending invalidate to be applied after the response
290 // comes back (but before this target is processed)
291 // - this target requires an exclusive block and either we're not
292 // getting an exclusive block back or we have already snooped
293 // another read request that will downgrade our exclusive block
294 // to shared
286
287 // assume we'd never issue a prefetch when we've got an
288 // outstanding miss
289 assert(pkt->cmd != MemCmd::HardPFReq);
290
295 if (inService &&
296 (!deferredTargets.empty() || hasPostInvalidate() ||
297 (pkt->needsExclusive() &&
298 (!isPendingDirty() || hasPostDowngrade() || isForward)))) {
299 // need to put on deferred list
300 if (hasPostInvalidate())
301 replaceUpgrade(pkt);
302 deferredTargets.add(pkt, whenReady, _order, Target::FromCPU, true);
303 } else {
304 // No request outstanding, or still OK to append to
305 // outstanding request: append to regular target list. Only
306 // mark pending if current request hasn't been issued yet
307 // (isn't in service).
308 targets.add(pkt, whenReady, _order, Target::FromCPU, !inService);
309 }
310}
311
312bool
313MSHR::handleSnoop(PacketPtr pkt, Counter _order)
314{
315 DPRINTF(Cache, "%s for %s addr %#llx size %d\n", __func__,
316 pkt->cmdString(), pkt->getAddr(), pkt->getSize());
317 if (!inService || (pkt->isExpressSnoop() && downstreamPending)) {
318 // Request has not been issued yet, or it's been issued
319 // locally but is buffered unissued at some downstream cache
320 // which is forwarding us this snoop. Either way, the packet
321 // we're snooping logically precedes this MSHR's request, so
322 // the snoop has no impact on the MSHR, but must be processed
323 // in the standard way by the cache. The only exception is
324 // that if we're an L2+ cache buffering an UpgradeReq from a
325 // higher-level cache, and the snoop is invalidating, then our
326 // buffered upgrades must be converted to read exclusives,
327 // since the upper-level cache no longer has a valid copy.
328 // That is, even though the upper-level cache got out on its
329 // local bus first, some other invalidating transaction
330 // reached the global bus before the upgrade did.
331 if (pkt->needsExclusive()) {
332 targets.replaceUpgrades();
333 deferredTargets.replaceUpgrades();
334 }
335
336 return false;
337 }
338
339 // From here on down, the request issued by this MSHR logically
340 // precedes the request we're snooping.
341 if (pkt->needsExclusive()) {
342 // snooped request still precedes the re-request we'll have to
343 // issue for deferred targets, if any...
344 deferredTargets.replaceUpgrades();
345 }
346
347 if (hasPostInvalidate()) {
348 // a prior snoop has already appended an invalidation, so
349 // logically we don't have the block anymore; no need for
350 // further snooping.
351 return true;
352 }
353
354 if (isPendingDirty() || pkt->isInvalidate()) {
355 // We need to save and replay the packet in two cases:
356 // 1. We're awaiting an exclusive copy, so ownership is pending,
357 // and we need to respond after we receive data.
358 // 2. It's an invalidation (e.g., UpgradeReq), and we need
359 // to forward the snoop up the hierarchy after the current
360 // transaction completes.
361
362 // Actual target device (typ. a memory) will delete the
363 // packet on reception, so we need to save a copy here.
364
365 // Clear flags and also allocate new data as the original
366 // packet data storage may have been deleted by the time we
367 // get to send this packet.
368 PacketPtr cp_pkt = new Packet(pkt, true, true);
369 targets.add(cp_pkt, curTick(), _order, Target::FromSnoop,
370 downstreamPending && targets.needsExclusive);
371
372 if (isPendingDirty()) {
373 pkt->assertMemInhibit();
374 pkt->setSupplyExclusive();
375 }
376
377 if (pkt->needsExclusive()) {
378 // This transaction will take away our pending copy
379 postInvalidate = true;
380 }
381 }
382
383 if (!pkt->needsExclusive()) {
384 // This transaction will get a read-shared copy, downgrading
385 // our copy if we had an exclusive one
386 postDowngrade = true;
387 pkt->assertShared();
388 }
389
390 return true;
391}
392
393
394bool
395MSHR::promoteDeferredTargets()
396{
397 assert(targets.empty());
398 if (deferredTargets.empty()) {
399 return false;
400 }
401
402 // swap targets & deferredTargets lists
403 std::swap(targets, deferredTargets);
404
405 // clear deferredTargets flags
406 deferredTargets.resetFlags();
407
408 order = targets.front().order;
409 readyTime = std::max(curTick(), targets.front().readyTime);
410
411 return true;
412}
413
414
415void
416MSHR::handleFill(PacketPtr pkt, CacheBlk *blk)
417{
418 if (!pkt->sharedAsserted()
419 && !(hasPostInvalidate() || hasPostDowngrade())
420 && deferredTargets.needsExclusive) {
421 // We got an exclusive response, but we have deferred targets
422 // which are waiting to request an exclusive copy (not because
423 // of a pending invalidate). This can happen if the original
424 // request was for a read-only (non-exclusive) block, but we
425 // got an exclusive copy anyway because of the E part of the
426 // MOESI/MESI protocol. Since we got the exclusive copy
427 // there's no need to defer the targets, so move them up to
428 // the regular target list.
429 assert(!targets.needsExclusive);
430 targets.needsExclusive = true;
431 // if any of the deferred targets were upper-level cache
432 // requests marked downstreamPending, need to clear that
433 assert(!downstreamPending); // not pending here anymore
434 deferredTargets.clearDownstreamPending();
435 // this clears out deferredTargets too
436 targets.splice(targets.end(), deferredTargets);
437 deferredTargets.resetFlags();
438 }
439}
440
441
442bool
443MSHR::checkFunctional(PacketPtr pkt)
444{
445 // For printing, we treat the MSHR as a whole as single entity.
446 // For other requests, we iterate over the individual targets
447 // since that's where the actual data lies.
448 if (pkt->isPrint()) {
449 pkt->checkFunctional(this, blkAddr, isSecure, blkSize, NULL);
450 return false;
451 } else {
452 return (targets.checkFunctional(pkt) ||
453 deferredTargets.checkFunctional(pkt));
454 }
455}
456
457
458void
459MSHR::print(std::ostream &os, int verbosity, const std::string &prefix) const
460{
461 ccprintf(os, "%s[%#llx:%#llx](%s) %s %s %s state: %s %s %s %s %s\n",
462 prefix, blkAddr, blkAddr + blkSize - 1,
463 isSecure ? "s" : "ns",
464 isForward ? "Forward" : "",
465 isForwardNoResponse() ? "ForwNoResp" : "",
466 needsExclusive() ? "Excl" : "",
467 _isUncacheable ? "Unc" : "",
468 inService ? "InSvc" : "",
469 downstreamPending ? "DwnPend" : "",
470 hasPostInvalidate() ? "PostInv" : "",
471 hasPostDowngrade() ? "PostDowngr" : "");
472
473 ccprintf(os, "%s Targets:\n", prefix);
474 targets.print(os, verbosity, prefix + " ");
475 if (!deferredTargets.empty()) {
476 ccprintf(os, "%s Deferred Targets:\n", prefix);
477 deferredTargets.print(os, verbosity, prefix + " ");
478 }
479}
480
481std::string
482MSHR::print() const
483{
484 ostringstream str;
485 print(str);
486 return str.str();
487}