1/*
2 * Copyright (c) 2012-2013, 2015-2017 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated

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460 TargetList ready_targets;
461 // If the downstream MSHR got an invalidation request then we only
462 // service the first of the FromCPU targets and any other
463 // non-FromCPU target. This way the remaining FromCPU targets
464 // issue a new request and get a fresh copy of the block and we
465 // avoid memory consistency violations.
466 if (pkt->cmd == MemCmd::ReadRespWithInvalidate) {
467 auto it = targets.begin();
468 assert((it->source == Target::FromCPU) ||
469 (it->source == Target::FromPrefetcher));
470 ready_targets.push_back(*it);
471 it = targets.erase(it);
472 while (it != targets.end()) {
473 if (it->source == Target::FromCPU) {
474 it++;
475 } else {
476 assert(it->source == Target::FromSnoop);
477 ready_targets.push_back(*it);

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