1/*
2 * Copyright (c) 2018 Inria
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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35 * line.
36 */
37
38#ifndef __MEM_CACHE_COMPRESSORS_BASE_HH__
39#define __MEM_CACHE_COMPRESSORS_BASE_HH__
40
41#include <cstdint>
42
43#include "base/types.hh"
44#include "sim/sim_object.hh"
45
46class CacheBlk;
47struct BaseCacheCompressorParams;
48
49/**
50 * Base cache compressor interface. Every cache compressor must implement a

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59 class CompressionData;
60
61 /**
62 * Uncompressed cache line size (in bytes).
63 */
64 const std::size_t blkSize;
65
66 /**
67 * Apply the compression process to the cache line.
68 * Returns the number of cycles used by the compressor, however it is
69 * usually covered by a good pipelined execution, and is currently ignored.
70 * The decompression latency is also returned, in order to avoid
71 * increasing simulation time and memory consumption.
72 *
73 * @param cache_line The cache line to be compressed.
74 * @param comp_lat Compression latency in number of cycles.

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131
132 /**
133 * Set the size of the compressed block, in bits.
134 *
135 * @param blk The compressed block.
136 * @param size_bits The block size.
137 */
138 static void setSizeBits(CacheBlk* blk, const std::size_t size_bits);
139};
140
141class BaseCacheCompressor::CompressionData {
142 private:
143 /**
144 * Compressed cache line size (in bits).
145 */
146 std::size_t _size;

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