cache_blk.hh (13445:070fc4d948c0) cache_blk.hh (13477:044307c0d0b8)
1/*
2 * Copyright (c) 2012-2018 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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100 uint8_t *data;
101
102 /** block state: OR of CacheBlkStatusBit */
103 typedef unsigned State;
104
105 /** The current status of this block. @sa CacheBlockStatusBits */
106 State status;
107
1/*
2 * Copyright (c) 2012-2018 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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100 uint8_t *data;
101
102 /** block state: OR of CacheBlkStatusBit */
103 typedef unsigned State;
104
105 /** The current status of this block. @sa CacheBlockStatusBits */
106 State status;
107
108 /** Which curTick() will this block be accessible */
108 /**
109 * Which curTick() will this block be accessible. Its value is only
110 * meaningful if the block is valid.
111 */
109 Tick whenReady;
110
111 /** Number of references to this block since it was brought in. */
112 unsigned refCount;
113
114 /** holds the source requestor ID for this block. */
115 int srcMasterId;
116
112 Tick whenReady;
113
114 /** Number of references to this block since it was brought in. */
115 unsigned refCount;
116
117 /** holds the source requestor ID for this block. */
118 int srcMasterId;
119
117 /** Tick on which the block was inserted in the cache. */
120 /**
121 * Tick on which the block was inserted in the cache. Its value is only
122 * meaningful if the block is valid.
123 */
118 Tick tickInserted;
119
120 protected:
121 /**
122 * Represents that the indicated thread context has a "lock" on
123 * the block, in the LL/SC sense.
124 */
125 class Lock {

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155 }
156 };
157
158 /** List of thread contexts that have performed a load-locked (LL)
159 * on the block since the last store. */
160 std::list<Lock> lockList;
161
162 public:
124 Tick tickInserted;
125
126 protected:
127 /**
128 * Represents that the indicated thread context has a "lock" on
129 * the block, in the LL/SC sense.
130 */
131 class Lock {

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161 }
162 };
163
164 /** List of thread contexts that have performed a load-locked (LL)
165 * on the block since the last store. */
166 std::list<Lock> lockList;
167
168 public:
163 CacheBlk() : data(nullptr)
169 CacheBlk() : data(nullptr), tickInserted(0)
164 {
165 invalidate();
166 }
167
168 CacheBlk(const CacheBlk&) = delete;
169 CacheBlk& operator=(const CacheBlk&) = delete;
170 virtual ~CacheBlk() {};
171

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206 virtual void invalidate()
207 {
208 tag = MaxAddr;
209 task_id = ContextSwitchTaskId::Unknown;
210 status = 0;
211 whenReady = MaxTick;
212 refCount = 0;
213 srcMasterId = Request::invldMasterId;
170 {
171 invalidate();
172 }
173
174 CacheBlk(const CacheBlk&) = delete;
175 CacheBlk& operator=(const CacheBlk&) = delete;
176 virtual ~CacheBlk() {};
177

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212 virtual void invalidate()
213 {
214 tag = MaxAddr;
215 task_id = ContextSwitchTaskId::Unknown;
216 status = 0;
217 whenReady = MaxTick;
218 refCount = 0;
219 srcMasterId = Request::invldMasterId;
214 tickInserted = MaxTick;
215 lockList.clear();
216 }
217
218 /**
219 * Check to see if a block has been written.
220 * @return True if the block is dirty.
221 */
222 bool isDirty() const

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256 * Set secure bit.
257 */
258 virtual void setSecure()
259 {
260 status |= BlkSecure;
261 }
262
263 /**
220 lockList.clear();
221 }
222
223 /**
224 * Check to see if a block has been written.
225 * @return True if the block is dirty.
226 */
227 bool isDirty() const

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261 * Set secure bit.
262 */
263 virtual void setSecure()
264 {
265 status |= BlkSecure;
266 }
267
268 /**
269 * Get tick at which block's data will be available for access.
270 *
271 * @return Data ready tick.
272 */
273 Tick getWhenReady() const
274 {
275 return whenReady;
276 }
277
278 /**
279 * Set tick at which block's data will be available for access. The new
280 * tick must be chronologically sequential with respect to previous
281 * accesses.
282 *
283 * @param tick New data ready tick.
284 */
285 void setWhenReady(const Tick tick)
286 {
287 assert((whenReady == MaxTick) || (tick >= whenReady));
288 assert(tick >= tickInserted);
289 whenReady = tick;
290 }
291
292 /**
264 * Set member variables when a block insertion occurs. Resets reference
265 * count to 1 (the insertion counts as a reference), and touch block if
266 * it hadn't been touched previously. Sets the insertion tick to the
267 * current tick. Marks the block valid.
268 *
269 * @param tag Block address tag.
270 * @param is_secure Whether the block is in secure space or not.
271 * @param src_master_ID The source requestor ID.

--- 216 unchanged lines hidden --- 		293 * Set member variables when a block insertion occurs. Resets reference
294 * count to 1 (the insertion counts as a reference), and touch block if
295 * it hadn't been touched previously. Sets the insertion tick to the
296 * current tick. Marks the block valid.
297 *
298 * @param tag Block address tag.
299 * @param is_secure Whether the block is in secure space or not.
300 * @param src_master_ID The source requestor ID.

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