cache_blk.hh (13477:044307c0d0b8) cache_blk.hh (13485:12e16073f6a7)
1/*
2 * Copyright (c) 2012-2018 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2003-2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Erik Hallnor
41 * Andreas Sandberg
42 */
43
44/** @file
45 * Definitions of a simple cache block class.
46 */
47
48#ifndef __MEM_CACHE_CACHE_BLK_HH__
49#define __MEM_CACHE_CACHE_BLK_HH__
50
51#include <cassert>
52#include <cstdint>
53#include <iosfwd>
54#include <list>
55#include <string>
56
57#include "base/printable.hh"
58#include "base/types.hh"
59#include "mem/cache/replacement_policies/base.hh"
60#include "mem/packet.hh"
61#include "mem/request.hh"
62
63/**
64 * Cache block status bit assignments
65 */
66enum CacheBlkStatusBits : unsigned {
67 /** valid, readable */
68 BlkValid = 0x01,
69 /** write permission */
70 BlkWritable = 0x02,
71 /** read permission (yes, block can be valid but not readable) */
72 BlkReadable = 0x04,
73 /** dirty (modified) */
74 BlkDirty = 0x08,
75 /** block was a hardware prefetch yet unaccessed*/
76 BlkHWPrefetched = 0x20,
77 /** block holds data from the secure memory space */
78 BlkSecure = 0x40,
79};
80
81/**
82 * A Basic Cache block.
83 * Contains the tag, status, and a pointer to data.
84 */
85class CacheBlk : public ReplaceableEntry
86{
87 public:
88 /** Task Id associated with this block */
89 uint32_t task_id;
90
91 /** Data block tag value. */
92 Addr tag;
93 /**
94 * Contains a copy of the data in this block for easy access. This is used
95 * for efficient execution when the data could be actually stored in
96 * another format (COW, compressed, sub-blocked, etc). In all cases the
97 * data stored here should be kept consistant with the actual data
98 * referenced by this block.
99 */
100 uint8_t *data;
101
102 /** block state: OR of CacheBlkStatusBit */
103 typedef unsigned State;
104
105 /** The current status of this block. @sa CacheBlockStatusBits */
106 State status;
107
108 /**
109 * Which curTick() will this block be accessible. Its value is only
110 * meaningful if the block is valid.
111 */
112 Tick whenReady;
113
114 /** Number of references to this block since it was brought in. */
115 unsigned refCount;
116
117 /** holds the source requestor ID for this block. */
118 int srcMasterId;
119
120 /**
121 * Tick on which the block was inserted in the cache. Its value is only
122 * meaningful if the block is valid.
123 */
124 Tick tickInserted;
125
126 protected:
127 /**
128 * Represents that the indicated thread context has a "lock" on
129 * the block, in the LL/SC sense.
130 */
131 class Lock {
132 public:
133 ContextID contextId; // locking context
134 Addr lowAddr; // low address of lock range
135 Addr highAddr; // high address of lock range
136
137 // check for matching execution context, and an address that
138 // is within the lock
139 bool matches(const RequestPtr &req) const
140 {
141 Addr req_low = req->getPaddr();
142 Addr req_high = req_low + req->getSize() -1;
143 return (contextId == req->contextId()) &&
144 (req_low >= lowAddr) && (req_high <= highAddr);
145 }
146
147 // check if a request is intersecting and thus invalidating the lock
148 bool intersects(const RequestPtr &req) const
149 {
150 Addr req_low = req->getPaddr();
151 Addr req_high = req_low + req->getSize() - 1;
152
153 return (req_low <= highAddr) && (req_high >= lowAddr);
154 }
155
156 Lock(const RequestPtr &req)
157 : contextId(req->contextId()),
158 lowAddr(req->getPaddr()),
159 highAddr(lowAddr + req->getSize() - 1)
160 {
161 }
162 };
163
164 /** List of thread contexts that have performed a load-locked (LL)
165 * on the block since the last store. */
166 std::list<Lock> lockList;
167
168 public:
169 CacheBlk() : data(nullptr), tickInserted(0)
170 {
171 invalidate();
172 }
173
174 CacheBlk(const CacheBlk&) = delete;
175 CacheBlk& operator=(const CacheBlk&) = delete;
176 virtual ~CacheBlk() {};
177
178 /**
179 * Checks the write permissions of this block.
180 * @return True if the block is writable.
181 */
182 bool isWritable() const
183 {
184 const State needed_bits = BlkWritable | BlkValid;
185 return (status & needed_bits) == needed_bits;
186 }
187
188 /**
189 * Checks the read permissions of this block. Note that a block
190 * can be valid but not readable if there is an outstanding write
191 * upgrade miss.
192 * @return True if the block is readable.
193 */
194 bool isReadable() const
195 {
196 const State needed_bits = BlkReadable | BlkValid;
197 return (status & needed_bits) == needed_bits;
198 }
199
200 /**
201 * Checks that a block is valid.
202 * @return True if the block is valid.
203 */
204 bool isValid() const
205 {
206 return (status & BlkValid) != 0;
207 }
208
209 /**
210 * Invalidate the block and clear all state.
211 */
212 virtual void invalidate()
213 {
214 tag = MaxAddr;
215 task_id = ContextSwitchTaskId::Unknown;
216 status = 0;
217 whenReady = MaxTick;
218 refCount = 0;
219 srcMasterId = Request::invldMasterId;
220 lockList.clear();
221 }
222
223 /**
224 * Check to see if a block has been written.
225 * @return True if the block is dirty.
226 */
227 bool isDirty() const
228 {
229 return (status & BlkDirty) != 0;
230 }
231
232 /**
233 * Check if this block was the result of a hardware prefetch, yet to
234 * be touched.
235 * @return True if the block was a hardware prefetch, unaccesed.
236 */
237 bool wasPrefetched() const
238 {
239 return (status & BlkHWPrefetched) != 0;
240 }
241
242 /**
243 * Check if this block holds data from the secure memory space.
244 * @return True if the block holds data from the secure memory space.
245 */
246 bool isSecure() const
247 {
248 return (status & BlkSecure) != 0;
249 }
250
251 /**
252 * Set valid bit.
253 */
254 virtual void setValid()
255 {
256 assert(!isValid());
257 status |= BlkValid;
258 }
259
260 /**
261 * Set secure bit.
262 */
263 virtual void setSecure()
264 {
265 status |= BlkSecure;
266 }
267
268 /**
269 * Get tick at which block's data will be available for access.
270 *
271 * @return Data ready tick.
272 */
273 Tick getWhenReady() const
274 {
275 return whenReady;
276 }
277
278 /**
279 * Set tick at which block's data will be available for access. The new
280 * tick must be chronologically sequential with respect to previous
281 * accesses.
282 *
283 * @param tick New data ready tick.
284 */
285 void setWhenReady(const Tick tick)
286 {
1/*
2 * Copyright (c) 2012-2018 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2003-2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Erik Hallnor
41 * Andreas Sandberg
42 */
43
44/** @file
45 * Definitions of a simple cache block class.
46 */
47
48#ifndef __MEM_CACHE_CACHE_BLK_HH__
49#define __MEM_CACHE_CACHE_BLK_HH__
50
51#include <cassert>
52#include <cstdint>
53#include <iosfwd>
54#include <list>
55#include <string>
56
57#include "base/printable.hh"
58#include "base/types.hh"
59#include "mem/cache/replacement_policies/base.hh"
60#include "mem/packet.hh"
61#include "mem/request.hh"
62
63/**
64 * Cache block status bit assignments
65 */
66enum CacheBlkStatusBits : unsigned {
67 /** valid, readable */
68 BlkValid = 0x01,
69 /** write permission */
70 BlkWritable = 0x02,
71 /** read permission (yes, block can be valid but not readable) */
72 BlkReadable = 0x04,
73 /** dirty (modified) */
74 BlkDirty = 0x08,
75 /** block was a hardware prefetch yet unaccessed*/
76 BlkHWPrefetched = 0x20,
77 /** block holds data from the secure memory space */
78 BlkSecure = 0x40,
79};
80
81/**
82 * A Basic Cache block.
83 * Contains the tag, status, and a pointer to data.
84 */
85class CacheBlk : public ReplaceableEntry
86{
87 public:
88 /** Task Id associated with this block */
89 uint32_t task_id;
90
91 /** Data block tag value. */
92 Addr tag;
93 /**
94 * Contains a copy of the data in this block for easy access. This is used
95 * for efficient execution when the data could be actually stored in
96 * another format (COW, compressed, sub-blocked, etc). In all cases the
97 * data stored here should be kept consistant with the actual data
98 * referenced by this block.
99 */
100 uint8_t *data;
101
102 /** block state: OR of CacheBlkStatusBit */
103 typedef unsigned State;
104
105 /** The current status of this block. @sa CacheBlockStatusBits */
106 State status;
107
108 /**
109 * Which curTick() will this block be accessible. Its value is only
110 * meaningful if the block is valid.
111 */
112 Tick whenReady;
113
114 /** Number of references to this block since it was brought in. */
115 unsigned refCount;
116
117 /** holds the source requestor ID for this block. */
118 int srcMasterId;
119
120 /**
121 * Tick on which the block was inserted in the cache. Its value is only
122 * meaningful if the block is valid.
123 */
124 Tick tickInserted;
125
126 protected:
127 /**
128 * Represents that the indicated thread context has a "lock" on
129 * the block, in the LL/SC sense.
130 */
131 class Lock {
132 public:
133 ContextID contextId; // locking context
134 Addr lowAddr; // low address of lock range
135 Addr highAddr; // high address of lock range
136
137 // check for matching execution context, and an address that
138 // is within the lock
139 bool matches(const RequestPtr &req) const
140 {
141 Addr req_low = req->getPaddr();
142 Addr req_high = req_low + req->getSize() -1;
143 return (contextId == req->contextId()) &&
144 (req_low >= lowAddr) && (req_high <= highAddr);
145 }
146
147 // check if a request is intersecting and thus invalidating the lock
148 bool intersects(const RequestPtr &req) const
149 {
150 Addr req_low = req->getPaddr();
151 Addr req_high = req_low + req->getSize() - 1;
152
153 return (req_low <= highAddr) && (req_high >= lowAddr);
154 }
155
156 Lock(const RequestPtr &req)
157 : contextId(req->contextId()),
158 lowAddr(req->getPaddr()),
159 highAddr(lowAddr + req->getSize() - 1)
160 {
161 }
162 };
163
164 /** List of thread contexts that have performed a load-locked (LL)
165 * on the block since the last store. */
166 std::list<Lock> lockList;
167
168 public:
169 CacheBlk() : data(nullptr), tickInserted(0)
170 {
171 invalidate();
172 }
173
174 CacheBlk(const CacheBlk&) = delete;
175 CacheBlk& operator=(const CacheBlk&) = delete;
176 virtual ~CacheBlk() {};
177
178 /**
179 * Checks the write permissions of this block.
180 * @return True if the block is writable.
181 */
182 bool isWritable() const
183 {
184 const State needed_bits = BlkWritable | BlkValid;
185 return (status & needed_bits) == needed_bits;
186 }
187
188 /**
189 * Checks the read permissions of this block. Note that a block
190 * can be valid but not readable if there is an outstanding write
191 * upgrade miss.
192 * @return True if the block is readable.
193 */
194 bool isReadable() const
195 {
196 const State needed_bits = BlkReadable | BlkValid;
197 return (status & needed_bits) == needed_bits;
198 }
199
200 /**
201 * Checks that a block is valid.
202 * @return True if the block is valid.
203 */
204 bool isValid() const
205 {
206 return (status & BlkValid) != 0;
207 }
208
209 /**
210 * Invalidate the block and clear all state.
211 */
212 virtual void invalidate()
213 {
214 tag = MaxAddr;
215 task_id = ContextSwitchTaskId::Unknown;
216 status = 0;
217 whenReady = MaxTick;
218 refCount = 0;
219 srcMasterId = Request::invldMasterId;
220 lockList.clear();
221 }
222
223 /**
224 * Check to see if a block has been written.
225 * @return True if the block is dirty.
226 */
227 bool isDirty() const
228 {
229 return (status & BlkDirty) != 0;
230 }
231
232 /**
233 * Check if this block was the result of a hardware prefetch, yet to
234 * be touched.
235 * @return True if the block was a hardware prefetch, unaccesed.
236 */
237 bool wasPrefetched() const
238 {
239 return (status & BlkHWPrefetched) != 0;
240 }
241
242 /**
243 * Check if this block holds data from the secure memory space.
244 * @return True if the block holds data from the secure memory space.
245 */
246 bool isSecure() const
247 {
248 return (status & BlkSecure) != 0;
249 }
250
251 /**
252 * Set valid bit.
253 */
254 virtual void setValid()
255 {
256 assert(!isValid());
257 status |= BlkValid;
258 }
259
260 /**
261 * Set secure bit.
262 */
263 virtual void setSecure()
264 {
265 status |= BlkSecure;
266 }
267
268 /**
269 * Get tick at which block's data will be available for access.
270 *
271 * @return Data ready tick.
272 */
273 Tick getWhenReady() const
274 {
275 return whenReady;
276 }
277
278 /**
279 * Set tick at which block's data will be available for access. The new
280 * tick must be chronologically sequential with respect to previous
281 * accesses.
282 *
283 * @param tick New data ready tick.
284 */
285 void setWhenReady(const Tick tick)
286 {
287 assert((whenReady == MaxTick) || (tick >= whenReady));
288 assert(tick >= tickInserted);
289 whenReady = tick;
290 }
291
292 /**
293 * Set member variables when a block insertion occurs. Resets reference
294 * count to 1 (the insertion counts as a reference), and touch block if
295 * it hadn't been touched previously. Sets the insertion tick to the
296 * current tick. Marks the block valid.
297 *
298 * @param tag Block address tag.
299 * @param is_secure Whether the block is in secure space or not.
300 * @param src_master_ID The source requestor ID.
301 * @param task_ID The new task ID.
302 */
303 virtual void insert(const Addr tag, const bool is_secure,
304 const int src_master_ID, const uint32_t task_ID);
305
306 /**
307 * Track the fact that a local locked was issued to the
308 * block. Invalidate any previous LL to the same address.
309 */
310 void trackLoadLocked(PacketPtr pkt)
311 {
312 assert(pkt->isLLSC());
313 auto l = lockList.begin();
314 while (l != lockList.end()) {
315 if (l->intersects(pkt->req))
316 l = lockList.erase(l);
317 else
318 ++l;
319 }
320
321 lockList.emplace_front(pkt->req);
322 }
323
324 /**
325 * Clear the any load lock that intersect the request, and is from
326 * a different context.
327 */
328 void clearLoadLocks(const RequestPtr &req)
329 {
330 auto l = lockList.begin();
331 while (l != lockList.end()) {
332 if (l->intersects(req) && l->contextId != req->contextId()) {
333 l = lockList.erase(l);
334 } else {
335 ++l;
336 }
337 }
338 }
339
340 /**
341 * Pretty-print tag, set and way, and interpret state bits to readable form
342 * including mapping to a MOESI state.
343 *
344 * @return string with basic state information
345 */
346 virtual std::string print() const
347 {
348 /**
349 * state M O E S I
350 * writable 1 0 1 0 0
351 * dirty 1 1 0 0 0
352 * valid 1 1 1 1 0
353 *
354 * state writable dirty valid
355 * M 1 1 1
356 * O 0 1 1
357 * E 1 0 1
358 * S 0 0 1
359 * I 0 0 0
360 *
361 * Note that only one cache ever has a block in Modified or
362 * Owned state, i.e., only one cache owns the block, or
363 * equivalently has the BlkDirty bit set. However, multiple
364 * caches on the same path to memory can have a block in the
365 * Exclusive state (despite the name). Exclusive means this
366 * cache has the only copy at this level of the hierarchy,
367 * i.e., there may be copies in caches above this cache (in
368 * various states), but there are no peers that have copies on
369 * this branch of the hierarchy, and no caches at or above
370 * this level on any other branch have copies either.
371 **/
372 unsigned state = isWritable() << 2 | isDirty() << 1 | isValid();
373 char s = '?';
374 switch (state) {
375 case 0b111: s = 'M'; break;
376 case 0b011: s = 'O'; break;
377 case 0b101: s = 'E'; break;
378 case 0b001: s = 'S'; break;
379 case 0b000: s = 'I'; break;
380 default: s = 'T'; break; // @TODO add other types
381 }
382 return csprintf("state: %x (%c) valid: %d writable: %d readable: %d "
383 "dirty: %d | tag: %#x set: %#x way: %#x", status, s,
384 isValid(), isWritable(), isReadable(), isDirty(), tag,
385 getSet(), getWay());
386 }
387
388 /**
389 * Handle interaction of load-locked operations and stores.
390 * @return True if write should proceed, false otherwise. Returns
391 * false only in the case of a failed store conditional.
392 */
393 bool checkWrite(PacketPtr pkt)
394 {
395 assert(pkt->isWrite());
396
397 // common case
398 if (!pkt->isLLSC() && lockList.empty())
399 return true;
400
401 const RequestPtr &req = pkt->req;
402
403 if (pkt->isLLSC()) {
404 // it's a store conditional... have to check for matching
405 // load locked.
406 bool success = false;
407
408 auto l = lockList.begin();
409 while (!success && l != lockList.end()) {
410 if (l->matches(pkt->req)) {
411 // it's a store conditional, and as far as the
412 // memory system can tell, the requesting
413 // context's lock is still valid.
414 success = true;
415 lockList.erase(l);
416 } else {
417 ++l;
418 }
419 }
420
421 req->setExtraData(success ? 1 : 0);
422 // clear any intersected locks from other contexts (our LL
423 // should already have cleared them)
424 clearLoadLocks(req);
425 return success;
426 } else {
427 // a normal write, if there is any lock not from this
428 // context we clear the list, thus for a private cache we
429 // never clear locks on normal writes
430 clearLoadLocks(req);
431 return true;
432 }
433 }
434};
435
436/**
437 * Special instance of CacheBlk for use with tempBlk that deals with its
438 * block address regeneration.
439 * @sa Cache
440 */
441class TempCacheBlk final : public CacheBlk
442{
443 private:
444 /**
445 * Copy of the block's address, used to regenerate tempBlock's address.
446 */
447 Addr _addr;
448
449 public:
450 /**
451 * Creates a temporary cache block, with its own storage.
452 * @param size The size (in bytes) of this cache block.
453 */
454 TempCacheBlk(unsigned size) : CacheBlk()
455 {
456 data = new uint8_t[size];
457 }
458 TempCacheBlk(const TempCacheBlk&) = delete;
459 TempCacheBlk& operator=(const TempCacheBlk&) = delete;
460 ~TempCacheBlk() { delete [] data; };
461
462 /**
463 * Invalidate the block and clear all state.
464 */
465 void invalidate() override {
466 CacheBlk::invalidate();
467
468 _addr = MaxAddr;
469 }
470
471 void insert(const Addr addr, const bool is_secure,
472 const int src_master_ID=0, const uint32_t task_ID=0) override
473 {
474 // Make sure that the block has been properly invalidated
475 assert(status == 0);
476
477 // Set block address
478 _addr = addr;
479
480 // Set secure state
481 if (is_secure) {
482 setSecure();
483 }
484
485 // Validate block
486 setValid();
487 }
488
489 /**
490 * Get block's address.
491 *
492 * @return addr Address value.
493 */
494 Addr getAddr() const
495 {
496 return _addr;
497 }
498};
499
500/**
501 * Simple class to provide virtual print() method on cache blocks
502 * without allocating a vtable pointer for every single cache block.
503 * Just wrap the CacheBlk object in an instance of this before passing
504 * to a function that requires a Printable object.
505 */
506class CacheBlkPrintWrapper : public Printable
507{
508 CacheBlk *blk;
509 public:
510 CacheBlkPrintWrapper(CacheBlk *_blk) : blk(_blk) {}
511 virtual ~CacheBlkPrintWrapper() {}
512 void print(std::ostream &o, int verbosity = 0,
513 const std::string &prefix = "") const;
514};
515
516#endif //__MEM_CACHE_CACHE_BLK_HH__
287 assert(tick >= tickInserted);
288 whenReady = tick;
289 }
290
291 /**
292 * Set member variables when a block insertion occurs. Resets reference
293 * count to 1 (the insertion counts as a reference), and touch block if
294 * it hadn't been touched previously. Sets the insertion tick to the
295 * current tick. Marks the block valid.
296 *
297 * @param tag Block address tag.
298 * @param is_secure Whether the block is in secure space or not.
299 * @param src_master_ID The source requestor ID.
300 * @param task_ID The new task ID.
301 */
302 virtual void insert(const Addr tag, const bool is_secure,
303 const int src_master_ID, const uint32_t task_ID);
304
305 /**
306 * Track the fact that a local locked was issued to the
307 * block. Invalidate any previous LL to the same address.
308 */
309 void trackLoadLocked(PacketPtr pkt)
310 {
311 assert(pkt->isLLSC());
312 auto l = lockList.begin();
313 while (l != lockList.end()) {
314 if (l->intersects(pkt->req))
315 l = lockList.erase(l);
316 else
317 ++l;
318 }
319
320 lockList.emplace_front(pkt->req);
321 }
322
323 /**
324 * Clear the any load lock that intersect the request, and is from
325 * a different context.
326 */
327 void clearLoadLocks(const RequestPtr &req)
328 {
329 auto l = lockList.begin();
330 while (l != lockList.end()) {
331 if (l->intersects(req) && l->contextId != req->contextId()) {
332 l = lockList.erase(l);
333 } else {
334 ++l;
335 }
336 }
337 }
338
339 /**
340 * Pretty-print tag, set and way, and interpret state bits to readable form
341 * including mapping to a MOESI state.
342 *
343 * @return string with basic state information
344 */
345 virtual std::string print() const
346 {
347 /**
348 * state M O E S I
349 * writable 1 0 1 0 0
350 * dirty 1 1 0 0 0
351 * valid 1 1 1 1 0
352 *
353 * state writable dirty valid
354 * M 1 1 1
355 * O 0 1 1
356 * E 1 0 1
357 * S 0 0 1
358 * I 0 0 0
359 *
360 * Note that only one cache ever has a block in Modified or
361 * Owned state, i.e., only one cache owns the block, or
362 * equivalently has the BlkDirty bit set. However, multiple
363 * caches on the same path to memory can have a block in the
364 * Exclusive state (despite the name). Exclusive means this
365 * cache has the only copy at this level of the hierarchy,
366 * i.e., there may be copies in caches above this cache (in
367 * various states), but there are no peers that have copies on
368 * this branch of the hierarchy, and no caches at or above
369 * this level on any other branch have copies either.
370 **/
371 unsigned state = isWritable() << 2 | isDirty() << 1 | isValid();
372 char s = '?';
373 switch (state) {
374 case 0b111: s = 'M'; break;
375 case 0b011: s = 'O'; break;
376 case 0b101: s = 'E'; break;
377 case 0b001: s = 'S'; break;
378 case 0b000: s = 'I'; break;
379 default: s = 'T'; break; // @TODO add other types
380 }
381 return csprintf("state: %x (%c) valid: %d writable: %d readable: %d "
382 "dirty: %d | tag: %#x set: %#x way: %#x", status, s,
383 isValid(), isWritable(), isReadable(), isDirty(), tag,
384 getSet(), getWay());
385 }
386
387 /**
388 * Handle interaction of load-locked operations and stores.
389 * @return True if write should proceed, false otherwise. Returns
390 * false only in the case of a failed store conditional.
391 */
392 bool checkWrite(PacketPtr pkt)
393 {
394 assert(pkt->isWrite());
395
396 // common case
397 if (!pkt->isLLSC() && lockList.empty())
398 return true;
399
400 const RequestPtr &req = pkt->req;
401
402 if (pkt->isLLSC()) {
403 // it's a store conditional... have to check for matching
404 // load locked.
405 bool success = false;
406
407 auto l = lockList.begin();
408 while (!success && l != lockList.end()) {
409 if (l->matches(pkt->req)) {
410 // it's a store conditional, and as far as the
411 // memory system can tell, the requesting
412 // context's lock is still valid.
413 success = true;
414 lockList.erase(l);
415 } else {
416 ++l;
417 }
418 }
419
420 req->setExtraData(success ? 1 : 0);
421 // clear any intersected locks from other contexts (our LL
422 // should already have cleared them)
423 clearLoadLocks(req);
424 return success;
425 } else {
426 // a normal write, if there is any lock not from this
427 // context we clear the list, thus for a private cache we
428 // never clear locks on normal writes
429 clearLoadLocks(req);
430 return true;
431 }
432 }
433};
434
435/**
436 * Special instance of CacheBlk for use with tempBlk that deals with its
437 * block address regeneration.
438 * @sa Cache
439 */
440class TempCacheBlk final : public CacheBlk
441{
442 private:
443 /**
444 * Copy of the block's address, used to regenerate tempBlock's address.
445 */
446 Addr _addr;
447
448 public:
449 /**
450 * Creates a temporary cache block, with its own storage.
451 * @param size The size (in bytes) of this cache block.
452 */
453 TempCacheBlk(unsigned size) : CacheBlk()
454 {
455 data = new uint8_t[size];
456 }
457 TempCacheBlk(const TempCacheBlk&) = delete;
458 TempCacheBlk& operator=(const TempCacheBlk&) = delete;
459 ~TempCacheBlk() { delete [] data; };
460
461 /**
462 * Invalidate the block and clear all state.
463 */
464 void invalidate() override {
465 CacheBlk::invalidate();
466
467 _addr = MaxAddr;
468 }
469
470 void insert(const Addr addr, const bool is_secure,
471 const int src_master_ID=0, const uint32_t task_ID=0) override
472 {
473 // Make sure that the block has been properly invalidated
474 assert(status == 0);
475
476 // Set block address
477 _addr = addr;
478
479 // Set secure state
480 if (is_secure) {
481 setSecure();
482 }
483
484 // Validate block
485 setValid();
486 }
487
488 /**
489 * Get block's address.
490 *
491 * @return addr Address value.
492 */
493 Addr getAddr() const
494 {
495 return _addr;
496 }
497};
498
499/**
500 * Simple class to provide virtual print() method on cache blocks
501 * without allocating a vtable pointer for every single cache block.
502 * Just wrap the CacheBlk object in an instance of this before passing
503 * to a function that requires a Printable object.
504 */
505class CacheBlkPrintWrapper : public Printable
506{
507 CacheBlk *blk;
508 public:
509 CacheBlkPrintWrapper(CacheBlk *_blk) : blk(_blk) {}
510 virtual ~CacheBlkPrintWrapper() {}
511 void print(std::ostream &o, int verbosity = 0,
512 const std::string &prefix = "") const;
513};
514
515#endif //__MEM_CACHE_CACHE_BLK_HH__