cache.hh (9529:28d6d9663a7e) cache.hh (9548:63d36f7ef562)
1/*
2 * Copyright (c) 2012-2013 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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229 * @param pkt The memory request with the fill data.
230 * @param blk The cache block if it already exists.
231 * @param writebacks List for any writebacks that need to be performed.
232 * @return Pointer to the new cache block.
233 */
234 BlkType *handleFill(PacketPtr pkt, BlkType *blk,
235 PacketList &writebacks);
236
1/*
2 * Copyright (c) 2012-2013 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 220 unchanged lines hidden (view full) ---

229 * @param pkt The memory request with the fill data.
230 * @param blk The cache block if it already exists.
231 * @param writebacks List for any writebacks that need to be performed.
232 * @return Pointer to the new cache block.
233 */
234 BlkType *handleFill(PacketPtr pkt, BlkType *blk,
235 PacketList &writebacks);
236
237
238 /**
239 * Performs the access specified by the request.
240 * @param pkt The request to perform.
241 * @return The result of the access.
242 */
243 bool recvTimingReq(PacketPtr pkt);
244
245 /**
246 * Handles a response (cache line fill/write ack) from the bus.
247 * @param pkt The response packet
248 */
249 void recvTimingResp(PacketPtr pkt);
250
251 /**
252 * Snoops bus transactions to maintain coherence.
253 * @param pkt The current bus transaction.
254 */
255 void recvTimingSnoopReq(PacketPtr pkt);
256
257 /**
258 * Handle a snoop response.
259 * @param pkt Snoop response packet
260 */
261 void recvTimingSnoopResp(PacketPtr pkt);
262
263 /**
264 * Performs the access specified by the request.
265 * @param pkt The request to perform.
266 * @return The number of cycles required for the access.
267 */
268 Cycles recvAtomic(PacketPtr pkt);
269
270 /**
271 * Snoop for the provided request in the cache and return the estimated
272 * time of completion.
273 * @param pkt The memory request to snoop
274 * @return The number of cycles required for the snoop.
275 */
276 Cycles recvAtomicSnoop(PacketPtr pkt);
277
278 /**
279 * Performs the access specified by the request.
280 * @param pkt The request to perform.
281 * @param fromCpuSide from the CPU side port or the memory side port
282 */
283 void functionalAccess(PacketPtr pkt, bool fromCpuSide);
284
237 void satisfyCpuSideRequest(PacketPtr pkt, BlkType *blk,
238 bool deferred_response = false,
239 bool pending_downgrade = false);
240 bool satisfyMSHR(MSHR *mshr, PacketPtr pkt, BlkType *blk);
241
242 void doTimingSupplyResponse(PacketPtr req_pkt, uint8_t *blk_data,
243 bool already_copied, bool pending_inval);
244

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286 * since some architecture models don't implement cache
287 * maintenance operations. We won't even try to get a decent
288 * timing here since the line should have been flushed earlier by
289 * a cache maintenance operation.
290 */
291 void uncacheableFlush(PacketPtr pkt);
292
293 /**
285 void satisfyCpuSideRequest(PacketPtr pkt, BlkType *blk,
286 bool deferred_response = false,
287 bool pending_downgrade = false);
288 bool satisfyMSHR(MSHR *mshr, PacketPtr pkt, BlkType *blk);
289
290 void doTimingSupplyResponse(PacketPtr req_pkt, uint8_t *blk_data,
291 bool already_copied, bool pending_inval);
292

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334 * since some architecture models don't implement cache
335 * maintenance operations. We won't even try to get a decent
336 * timing here since the line should have been flushed earlier by
337 * a cache maintenance operation.
338 */
339 void uncacheableFlush(PacketPtr pkt);
340
341 /**
294 * Performs the access specified by the request.
295 * @param pkt The request to perform.
296 * @return The result of the access.
297 */
298 bool timingAccess(PacketPtr pkt);
299
300 /**
301 * Performs the access specified by the request.
302 * @param pkt The request to perform.
303 * @return The number of ticks required for the access.
304 */
305 Tick atomicAccess(PacketPtr pkt);
306
307 /**
308 * Performs the access specified by the request.
309 * @param pkt The request to perform.
310 * @param fromCpuSide from the CPU side port or the memory side port
311 */
312 void functionalAccess(PacketPtr pkt, bool fromCpuSide);
313
314 /**
315 * Handles a response (cache line fill/write ack) from the bus.
316 * @param pkt The request being responded to.
317 */
318 void handleResponse(PacketPtr pkt);
319
320 /**
321 * Snoops bus transactions to maintain coherence.
322 * @param pkt The current bus transaction.
323 */
324 void snoopTiming(PacketPtr pkt);
325
326 /**
327 * Snoop for the provided request in the cache and return the estimated
328 * time of completion.
329 * @param pkt The memory request to snoop
330 * @return The number of cycles required for the snoop.
331 */
332 Cycles snoopAtomic(PacketPtr pkt);
333
334 /**
335 * Squash all requests associated with specified thread.
336 * intended for use by I-cache.
337 * @param threadNum The thread to squash.
338 */
339 void squash(int threadNum);
340
341 /**
342 * Generate an appropriate downstream bus request packet for the

--- 74 unchanged lines hidden --- 		342 * Squash all requests associated with specified thread.
343 * intended for use by I-cache.
344 * @param threadNum The thread to squash.
345 */
346 void squash(int threadNum);
347
348 /**
349 * Generate an appropriate downstream bus request packet for the

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