cache.hh (9347:b02075171b57) cache.hh (9445:5963165c00cb)
1/*
2 * Copyright (c) 2012 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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273 * Cache block visitor that invalidates all blocks in the cache.
274 *
275 * @warn Dirty cache lines will not be written back to memory.
276 *
277 * \return Always returns true.
278 */
279 bool invalidateVisitor(BlkType &blk);
280
1/*
2 * Copyright (c) 2012 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 264 unchanged lines hidden (view full) ---

273 * Cache block visitor that invalidates all blocks in the cache.
274 *
275 * @warn Dirty cache lines will not be written back to memory.
276 *
277 * \return Always returns true.
278 */
279 bool invalidateVisitor(BlkType &blk);
280
281 /**
282 * Flush a cache line due to an uncacheable memory access to the
283 * line.
284 *
285 * @note This shouldn't normally happen, but we need to handle it
286 * since some architecture models don't implement cache
287 * maintenance operations. We won't even try to get a decent
288 * timing here since the line should have been flushed earlier by
289 * a cache maintenance operation.
290 */
291 void uncacheableFlush(PacketPtr pkt);
292
281 public:
282 /** Instantiates a basic cache object. */
283 Cache(const Params *p, TagStore *tags);
284
285 void regStats();
286
287 /**
288 * Performs the access specified by the request.

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293 public:
294 /** Instantiates a basic cache object. */
295 Cache(const Params *p, TagStore *tags);
296
297 void regStats();
298
299 /**
300 * Performs the access specified by the request.

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