cache.hh (8948:e95ee70f876c) cache.hh (8975:7f36d4436074)
1/*
2 * Copyright (c) 2012 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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85 {
86 private:
87
88 // a pointer to our specific cache implementation
89 Cache<TagStore> *cache;
90
91 protected:
92
1/*
2 * Copyright (c) 2012 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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85 {
86 private:
87
88 // a pointer to our specific cache implementation
89 Cache<TagStore> *cache;
90
91 protected:
92
93 virtual bool recvTimingSnoop(PacketPtr pkt);
93 virtual bool recvTimingSnoopResp(PacketPtr pkt);
94
94
95 virtual bool recvTiming(PacketPtr pkt);
95 virtual bool recvTimingReq(PacketPtr pkt);
96
97 virtual Tick recvAtomic(PacketPtr pkt);
98
99 virtual void recvFunctional(PacketPtr pkt);
100
101 virtual unsigned deviceBlockSize() const
102 { return cache->getBlockSize(); }
103

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111 };
112
113 /**
114 * Override the default behaviour of sendDeferredPacket to enable
115 * the memory-side cache port to also send requests based on the
116 * current MSHR status. This queue has a pointer to our specific
117 * cache implementation and is used by the MemSidePort.
118 */
96
97 virtual Tick recvAtomic(PacketPtr pkt);
98
99 virtual void recvFunctional(PacketPtr pkt);
100
101 virtual unsigned deviceBlockSize() const
102 { return cache->getBlockSize(); }
103

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111 };
112
113 /**
114 * Override the default behaviour of sendDeferredPacket to enable
115 * the memory-side cache port to also send requests based on the
116 * current MSHR status. This queue has a pointer to our specific
117 * cache implementation and is used by the MemSidePort.
118 */
119 class MemSidePacketQueue : public PacketQueue
119 class MemSidePacketQueue : public MasterPacketQueue
120 {
121
122 protected:
123
124 Cache<TagStore> &cache;
125
126 public:
127
120 {
121
122 protected:
123
124 Cache<TagStore> &cache;
125
126 public:
127
128 MemSidePacketQueue(Cache &cache, Port &port,
128 MemSidePacketQueue(Cache<TagStore> &cache, MasterPort &port,
129 const std::string &label) :
129 const std::string &label) :
130 PacketQueue(cache, port, label), cache(cache) { }
130 MasterPacketQueue(cache, port, label), cache(cache) { }
131
132 /**
133 * Override the normal sendDeferredPacket and do not only
134 * consider the transmit list (used for responses), but also
135 * requests.
136 */
137 virtual void sendDeferredPacket();
138

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149 /** The cache-specific queue. */
150 MemSidePacketQueue _queue;
151
152 // a pointer to our specific cache implementation
153 Cache<TagStore> *cache;
154
155 protected:
156
131
132 /**
133 * Override the normal sendDeferredPacket and do not only
134 * consider the transmit list (used for responses), but also
135 * requests.
136 */
137 virtual void sendDeferredPacket();
138

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149 /** The cache-specific queue. */
150 MemSidePacketQueue _queue;
151
152 // a pointer to our specific cache implementation
153 Cache<TagStore> *cache;
154
155 protected:
156
157 virtual bool recvTimingSnoop(PacketPtr pkt);
157 virtual void recvTimingSnoopReq(PacketPtr pkt);
158
158
159 virtual bool recvTiming(PacketPtr pkt);
159 virtual bool recvTimingResp(PacketPtr pkt);
160
161 virtual Tick recvAtomicSnoop(PacketPtr pkt);
162
163 virtual void recvFunctionalSnoop(PacketPtr pkt);
164
165 virtual unsigned deviceBlockSize() const
166 { return cache->getBlockSize(); }
167

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161 virtual Tick recvAtomicSnoop(PacketPtr pkt);
162
163 virtual void recvFunctionalSnoop(PacketPtr pkt);
164
165 virtual unsigned deviceBlockSize() const
166 { return cache->getBlockSize(); }
167

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