cache.hh (8856:241ee47b0dc6) cache.hh (8914:8c3bd7bea667)
1/*
2 * Copyright (c) 2012 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 95 unchanged lines hidden (view full) ---

104 public:
105
106 CpuSidePort(const std::string &_name, Cache<TagStore> *_cache,
107 const std::string &_label);
108
109 };
110
111 /**
1/*
2 * Copyright (c) 2012 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 95 unchanged lines hidden (view full) ---

104 public:
105
106 CpuSidePort(const std::string &_name, Cache<TagStore> *_cache,
107 const std::string &_label);
108
109 };
110
111 /**
112 * Override the default behaviour of sendDeferredPacket to enable
113 * the memory-side cache port to also send requests based on the
114 * current MSHR status. This queue has a pointer to our specific
115 * cache implementation and is used by the MemSidePort.
116 */
117 class MemSidePacketQueue : public PacketQueue
118 {
119
120 protected:
121
122 Cache<TagStore> &cache;
123
124 public:
125
126 MemSidePacketQueue(Cache<TagStore> &cache, Port &port,
127 const std::string &label) :
128 PacketQueue(cache, port, label), cache(cache) { }
129
130 /**
131 * Override the normal sendDeferredPacket and do not only
132 * consider the transmit list (used for responses), but also
133 * requests.
134 */
135 virtual void sendDeferredPacket();
136
137 };
138
139 /**
112 * The memory-side port extends the base cache master port with
113 * access functions for functional, atomic and timing snoops.
114 */
115 class MemSidePort : public CacheMasterPort
116 {
117 private:
118
140 * The memory-side port extends the base cache master port with
141 * access functions for functional, atomic and timing snoops.
142 */
143 class MemSidePort : public CacheMasterPort
144 {
145 private:
146
147 /** The cache-specific queue. */
148 MemSidePacketQueue _queue;
149
119 // a pointer to our specific cache implementation
120 Cache<TagStore> *cache;
121
122 protected:
123
124 virtual bool recvTiming(PacketPtr pkt);
125
126 virtual Tick recvAtomic(PacketPtr pkt);
127
128 virtual void recvFunctional(PacketPtr pkt);
129
130 virtual unsigned deviceBlockSize() const
131 { return cache->getBlockSize(); }
132
133 public:
134
135 MemSidePort(const std::string &_name, Cache<TagStore> *_cache,
136 const std::string &_label);
150 // a pointer to our specific cache implementation
151 Cache<TagStore> *cache;
152
153 protected:
154
155 virtual bool recvTiming(PacketPtr pkt);
156
157 virtual Tick recvAtomic(PacketPtr pkt);
158
159 virtual void recvFunctional(PacketPtr pkt);
160
161 virtual unsigned deviceBlockSize() const
162 { return cache->getBlockSize(); }
163
164 public:
165
166 MemSidePort(const std::string &_name, Cache<TagStore> *_cache,
167 const std::string &_label);
137
138 /**
139 * Overload sendDeferredPacket of SimpleTimingPort.
140 */
141 virtual void sendDeferredPacket();
142 };
143
144 /** Tag and data Storage */
145 TagStore *tags;
146
147 /** Prefetcher */
148 BasePrefetcher *prefetcher;
149

--- 198 unchanged lines hidden --- 		168 };
169
170 /** Tag and data Storage */
171 TagStore *tags;
172
173 /** Prefetcher */
174 BasePrefetcher *prefetcher;
175

--- 198 unchanged lines hidden ---