cache.hh (8831:6c08a877af8f) cache.hh (8856:241ee47b0dc6)
1/*
2 * Copyright (c) 2012 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 27 unchanged lines hidden (view full) ---

36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Erik Hallnor
41 * Dave Greene
42 * Steve Reinhardt
43 * Ron Dreslinski
1/*
2 * Copyright (c) 2012 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 27 unchanged lines hidden (view full) ---

36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Erik Hallnor
41 * Dave Greene
42 * Steve Reinhardt
43 * Ron Dreslinski
44 * Andreas Hansson
44 */
45
46/**
47 * @file
48 * Describes a cache based on template policies.
49 */
50
51#ifndef __CACHE_HH__

--- 19 unchanged lines hidden (view full) ---

71 public:
72 /** Define the type of cache block to use. */
73 typedef typename TagStore::BlkType BlkType;
74 /** A typedef for a list of BlkType pointers. */
75 typedef typename TagStore::BlkList BlkList;
76
77 protected:
78
45 */
46
47/**
48 * @file
49 * Describes a cache based on template policies.
50 */
51
52#ifndef __CACHE_HH__

--- 19 unchanged lines hidden (view full) ---

72 public:
73 /** Define the type of cache block to use. */
74 typedef typename TagStore::BlkType BlkType;
75 /** A typedef for a list of BlkType pointers. */
76 typedef typename TagStore::BlkList BlkList;
77
78 protected:
79
79 class CpuSidePort : public CachePort
80 /**
81 * The CPU-side port extends the base cache slave port with access
82 * functions for functional, atomic and timing requests.
83 */
84 class CpuSidePort : public CacheSlavePort
80 {
85 {
81 public:
82 CpuSidePort(const std::string &_name,
83 Cache<TagStore> *_cache,
84 const std::string &_label);
86 private:
85
87
86 // BaseCache::CachePort just has a BaseCache *; this function
87 // lets us get back the type info we lost when we stored the
88 // cache pointer there.
89 Cache<TagStore> *myCache() {
90 return static_cast<Cache<TagStore> *>(cache);
91 }
88 // a pointer to our specific cache implementation
89 Cache<TagStore> *cache;
92
90
93 virtual AddrRangeList getAddrRanges();
91 protected:
94
95 virtual bool recvTiming(PacketPtr pkt);
96
97 virtual Tick recvAtomic(PacketPtr pkt);
98
99 virtual void recvFunctional(PacketPtr pkt);
92
93 virtual bool recvTiming(PacketPtr pkt);
94
95 virtual Tick recvAtomic(PacketPtr pkt);
96
97 virtual void recvFunctional(PacketPtr pkt);
100 };
101
98
102 class MemSidePort : public CachePort
103 {
99 virtual unsigned deviceBlockSize() const
100 { return cache->getBlockSize(); }
101
102 virtual AddrRangeList getAddrRanges();
103
104 public:
104 public:
105 MemSidePort(const std::string &_name,
106 Cache<TagStore> *_cache,
105
106 CpuSidePort(const std::string &_name, Cache<TagStore> *_cache,
107 const std::string &_label);
108
107 const std::string &_label);
108
109 // BaseCache::CachePort just has a BaseCache *; this function
110 // lets us get back the type info we lost when we stored the
111 // cache pointer there.
112 Cache<TagStore> *myCache() {
113 return static_cast<Cache<TagStore> *>(cache);
114 }
109 };
115
110
116 void sendPacket();
111 /**
112 * The memory-side port extends the base cache master port with
113 * access functions for functional, atomic and timing snoops.
114 */
115 class MemSidePort : public CacheMasterPort
116 {
117 private:
117
118
118 void processSendEvent();
119 // a pointer to our specific cache implementation
120 Cache<TagStore> *cache;
119
121
120 virtual bool isSnooping();
122 protected:
121
122 virtual bool recvTiming(PacketPtr pkt);
123
123
124 virtual bool recvTiming(PacketPtr pkt);
125
124 virtual void recvRetry();
125
126 virtual Tick recvAtomic(PacketPtr pkt);
127
128 virtual void recvFunctional(PacketPtr pkt);
129
126 virtual Tick recvAtomic(PacketPtr pkt);
127
128 virtual void recvFunctional(PacketPtr pkt);
129
130 typedef EventWrapper<MemSidePort, &MemSidePort::processSendEvent>
131 SendEvent;
130 virtual unsigned deviceBlockSize() const
131 { return cache->getBlockSize(); }
132
133 public:
134
135 MemSidePort(const std::string &_name, Cache<TagStore> *_cache,
136 const std::string &_label);
137
138 /**
139 * Overload sendDeferredPacket of SimpleTimingPort.
140 */
141 virtual void sendDeferredPacket();
132 };
133
134 /** Tag and data Storage */
135 TagStore *tags;
136
137 /** Prefetcher */
138 BasePrefetcher *prefetcher;
139

--- 198 unchanged lines hidden --- 		142 };
143
144 /** Tag and data Storage */
145 TagStore *tags;
146
147 /** Prefetcher */
148 BasePrefetcher *prefetcher;
149

--- 198 unchanged lines hidden ---