cache.hh (5707:da86e00f87a0) | cache.hh (5875:d82be3235ab4) |
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1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 50 unchanged lines hidden (view full) --- 59class Cache : public BaseCache 60{ 61 public: 62 /** Define the type of cache block to use. */ 63 typedef typename TagStore::BlkType BlkType; 64 /** A typedef for a list of BlkType pointers. */ 65 typedef typename TagStore::BlkList BlkList; 66 | 1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 50 unchanged lines hidden (view full) --- 59class Cache : public BaseCache 60{ 61 public: 62 /** Define the type of cache block to use. */ 63 typedef typename TagStore::BlkType BlkType; 64 /** A typedef for a list of BlkType pointers. */ 65 typedef typename TagStore::BlkList BlkList; 66 |
67 bool prefetchAccess; 68 | |
69 protected: 70 71 class CpuSidePort : public CachePort 72 { 73 public: 74 CpuSidePort(const std::string &_name, 75 Cache<TagStore> *_cache, 76 const std::string &_label, --- 59 unchanged lines hidden (view full) --- 136 /** Temporary cache block for occasional transitory use */ 137 BlkType *tempBlock; 138 139 /** 140 * This cache should allocate a block on a line-sized write miss. 141 */ 142 const bool doFastWrites; 143 | 67 protected: 68 69 class CpuSidePort : public CachePort 70 { 71 public: 72 CpuSidePort(const std::string &_name, 73 Cache<TagStore> *_cache, 74 const std::string &_label, --- 59 unchanged lines hidden (view full) --- 134 /** Temporary cache block for occasional transitory use */ 135 BlkType *tempBlock; 136 137 /** 138 * This cache should allocate a block on a line-sized write miss. 139 */ 140 const bool doFastWrites; 141 |
144 const bool prefetchMiss; | 142 /** 143 * Notify the prefetcher on every access, not just misses. 144 */ 145 const bool prefetchOnAccess; |
145 146 /** 147 * Does all the processing necessary to perform the provided request. 148 * @param pkt The memory request to perform. 149 * @param lat The latency of the access. 150 * @param writebacks List for any writebacks that need to be performed. 151 * @param update True if the replacement data should be updated. 152 * @return Boolean indicating whether the request was satisfied. --- 162 unchanged lines hidden (view full) --- 315 316 bool inCache(Addr addr) { 317 return (tags->findBlock(addr) != 0); 318 } 319 320 bool inMissQueue(Addr addr) { 321 return (mshrQueue.findMatch(addr) != 0); 322 } | 146 147 /** 148 * Does all the processing necessary to perform the provided request. 149 * @param pkt The memory request to perform. 150 * @param lat The latency of the access. 151 * @param writebacks List for any writebacks that need to be performed. 152 * @param update True if the replacement data should be updated. 153 * @return Boolean indicating whether the request was satisfied. --- 162 unchanged lines hidden (view full) --- 316 317 bool inCache(Addr addr) { 318 return (tags->findBlock(addr) != 0); 319 } 320 321 bool inMissQueue(Addr addr) { 322 return (mshrQueue.findMatch(addr) != 0); 323 } |
324 325 /** 326 * Find next request ready time from among possible sources. 327 */ 328 Tick nextMSHRReadyTime(); |
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323}; 324 325#endif // __CACHE_HH__ | 329}; 330 331#endif // __CACHE_HH__ |