cache.hh (5034:6186ef720dd4) | cache.hh (5314:e902f12a3af1) |
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1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 59 unchanged lines hidden (view full) --- 68 69 protected: 70 71 class CpuSidePort : public CachePort 72 { 73 public: 74 CpuSidePort(const std::string &_name, 75 Cache<TagStore> *_cache, | 1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 59 unchanged lines hidden (view full) --- 68 69 protected: 70 71 class CpuSidePort : public CachePort 72 { 73 public: 74 CpuSidePort(const std::string &_name, 75 Cache<TagStore> *_cache, |
76 const std::string &_label, |
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76 std::vector<Range<Addr> > filterRanges); 77 78 // BaseCache::CachePort just has a BaseCache *; this function 79 // lets us get back the type info we lost when we stored the 80 // cache pointer there. 81 Cache<TagStore> *myCache() { 82 return static_cast<Cache<TagStore> *>(cache); 83 } --- 8 unchanged lines hidden (view full) --- 92 virtual void recvFunctional(PacketPtr pkt); 93 }; 94 95 class MemSidePort : public CachePort 96 { 97 public: 98 MemSidePort(const std::string &_name, 99 Cache<TagStore> *_cache, | 77 std::vector<Range<Addr> > filterRanges); 78 79 // BaseCache::CachePort just has a BaseCache *; this function 80 // lets us get back the type info we lost when we stored the 81 // cache pointer there. 82 Cache<TagStore> *myCache() { 83 return static_cast<Cache<TagStore> *>(cache); 84 } --- 8 unchanged lines hidden (view full) --- 93 virtual void recvFunctional(PacketPtr pkt); 94 }; 95 96 class MemSidePort : public CachePort 97 { 98 public: 99 MemSidePort(const std::string &_name, 100 Cache<TagStore> *_cache, |
101 const std::string &_label, |
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100 std::vector<Range<Addr> > filterRanges); 101 102 // BaseCache::CachePort just has a BaseCache *; this function 103 // lets us get back the type info we lost when we stored the 104 // cache pointer there. 105 Cache<TagStore> *myCache() { 106 return static_cast<Cache<TagStore> *>(cache); 107 } --- 116 unchanged lines hidden (view full) --- 224 */ 225 Tick atomicAccess(PacketPtr pkt); 226 227 /** 228 * Performs the access specified by the request. 229 * @param pkt The request to perform. 230 * @return The result of the access. 231 */ | 102 std::vector<Range<Addr> > filterRanges); 103 104 // BaseCache::CachePort just has a BaseCache *; this function 105 // lets us get back the type info we lost when we stored the 106 // cache pointer there. 107 Cache<TagStore> *myCache() { 108 return static_cast<Cache<TagStore> *>(cache); 109 } --- 116 unchanged lines hidden (view full) --- 226 */ 227 Tick atomicAccess(PacketPtr pkt); 228 229 /** 230 * Performs the access specified by the request. 231 * @param pkt The request to perform. 232 * @return The result of the access. 233 */ |
232 void functionalAccess(PacketPtr pkt, CachePort *otherSidePort); | 234 void functionalAccess(PacketPtr pkt, CachePort *incomingPort, 235 CachePort *otherSidePort); |
233 234 /** 235 * Handles a response (cache line fill/write ack) from the bus. 236 * @param pkt The request being responded to. 237 */ 238 void handleResponse(PacketPtr pkt); 239 240 /** --- 65 unchanged lines hidden --- | 236 237 /** 238 * Handles a response (cache line fill/write ack) from the bus. 239 * @param pkt The request being responded to. 240 */ 241 void handleResponse(PacketPtr pkt); 242 243 /** --- 65 unchanged lines hidden --- |