cache.hh (4670:54ac1fb49a26) | cache.hh (4671:5d29d3be0f79) |
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1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 122 unchanged lines hidden (view full) --- 131 TagStore *tags; 132 133 /** Coherence protocol. */ 134 Coherence *coherence; 135 136 /** Prefetcher */ 137 BasePrefetcher *prefetcher; 138 | 1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 122 unchanged lines hidden (view full) --- 131 TagStore *tags; 132 133 /** Coherence protocol. */ 134 Coherence *coherence; 135 136 /** Prefetcher */ 137 BasePrefetcher *prefetcher; 138 |
139 /** Temporary cache block for occasional transitory use */ 140 BlkType *tempBlock; 141 |
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139 /** 140 * Can this cache should allocate a block on a line-sized write miss. 141 */ 142 const bool doFastWrites; 143 144 const bool prefetchMiss; 145 146 /** --- 188 unchanged lines hidden --- | 142 /** 143 * Can this cache should allocate a block on a line-sized write miss. 144 */ 145 const bool doFastWrites; 146 147 const bool prefetchMiss; 148 149 /** --- 188 unchanged lines hidden --- |