cache.hh (4478:33c4bf0ab4b9) cache.hh (4626:ed8aacb19c03)
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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40#define __CACHE_HH__
41
42#include "base/compression/base.hh"
43#include "base/misc.hh" // fatal, panic, and warn
44#include "cpu/smt.hh" // SMT_MAX_THREADS
45
46#include "mem/cache/base_cache.hh"
47#include "mem/cache/cache_blk.hh"
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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40#define __CACHE_HH__
41
42#include "base/compression/base.hh"
43#include "base/misc.hh" // fatal, panic, and warn
44#include "cpu/smt.hh" // SMT_MAX_THREADS
45
46#include "mem/cache/base_cache.hh"
47#include "mem/cache/cache_blk.hh"
48#include "mem/cache/miss/miss_buffer.hh"
48#include "mem/cache/miss/mshr.hh"
49
50#include "sim/eventq.hh"
51
52//Forward decleration
49
50#include "sim/eventq.hh"
51
52//Forward decleration
53class MSHR;
54class BasePrefetcher;
55
56/**
57 * A template-policy based cache. The behavior of the cache can be altered by
58 * supplying different template policies. TagStore handles all tag and data
59 * storage @sa TagStore. Buffering handles all misses and writes/writebacks
60 * @sa MissQueue. Coherence handles all coherence policy details @sa
61 * UniCoherence, SimpleMultiCoherence.

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81
82 // BaseCache::CachePort just has a BaseCache *; this function
83 // lets us get back the type info we lost when we stored the
84 // cache pointer there.
85 Cache<TagStore,Coherence> *myCache() {
86 return static_cast<Cache<TagStore,Coherence> *>(cache);
87 }
88
53class BasePrefetcher;
54
55/**
56 * A template-policy based cache. The behavior of the cache can be altered by
57 * supplying different template policies. TagStore handles all tag and data
58 * storage @sa TagStore. Buffering handles all misses and writes/writebacks
59 * @sa MissQueue. Coherence handles all coherence policy details @sa
60 * UniCoherence, SimpleMultiCoherence.

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80
81 // BaseCache::CachePort just has a BaseCache *; this function
82 // lets us get back the type info we lost when we stored the
83 // cache pointer there.
84 Cache<TagStore,Coherence> *myCache() {
85 return static_cast<Cache<TagStore,Coherence> *>(cache);
86 }
87
89 void processRequestEvent();
90 void processResponseEvent();
91
92 virtual void getDeviceAddressRanges(AddrRangeList &resp,
93 bool &snoop);
94
95 virtual bool recvTiming(PacketPtr pkt);
96
88 virtual void getDeviceAddressRanges(AddrRangeList &resp,
89 bool &snoop);
90
91 virtual bool recvTiming(PacketPtr pkt);
92
97 virtual void recvRetry();
98
99 virtual Tick recvAtomic(PacketPtr pkt);
100
101 virtual void recvFunctional(PacketPtr pkt);
93 virtual Tick recvAtomic(PacketPtr pkt);
94
95 virtual void recvFunctional(PacketPtr pkt);
102
103 typedef EventWrapper<CpuSidePort, &CpuSidePort::processResponseEvent>
104 ResponseEvent;
105
106 typedef EventWrapper<CpuSidePort, &CpuSidePort::processRequestEvent>
107 RequestEvent;
108
109 virtual void scheduleRequestEvent(Tick t) {
110 new RequestEvent(this, t);
111 }
112 };
113
114 class MemSidePort : public CachePort
115 {
116 public:
117 MemSidePort(const std::string &_name,
118 Cache<TagStore,Coherence> *_cache);
119
120 // BaseCache::CachePort just has a BaseCache *; this function
121 // lets us get back the type info we lost when we stored the
122 // cache pointer there.
123 Cache<TagStore,Coherence> *myCache() {
124 return static_cast<Cache<TagStore,Coherence> *>(cache);
125 }
126
96 };
97
98 class MemSidePort : public CachePort
99 {
100 public:
101 MemSidePort(const std::string &_name,
102 Cache<TagStore,Coherence> *_cache);
103
104 // BaseCache::CachePort just has a BaseCache *; this function
105 // lets us get back the type info we lost when we stored the
106 // cache pointer there.
107 Cache<TagStore,Coherence> *myCache() {
108 return static_cast<Cache<TagStore,Coherence> *>(cache);
109 }
110
127 void processRequestEvent();
128 void processResponseEvent();
111 void sendPacket();
129
112
113 void processSendEvent();
114
130 virtual void getDeviceAddressRanges(AddrRangeList &resp,
131 bool &snoop);
132
133 virtual bool recvTiming(PacketPtr pkt);
134
135 virtual void recvRetry();
136
137 virtual Tick recvAtomic(PacketPtr pkt);
138
139 virtual void recvFunctional(PacketPtr pkt);
140
115 virtual void getDeviceAddressRanges(AddrRangeList &resp,
116 bool &snoop);
117
118 virtual bool recvTiming(PacketPtr pkt);
119
120 virtual void recvRetry();
121
122 virtual Tick recvAtomic(PacketPtr pkt);
123
124 virtual void recvFunctional(PacketPtr pkt);
125
141 typedef EventWrapper<MemSidePort, &MemSidePort::processResponseEvent>
142 ResponseEvent;
143
144 typedef EventWrapper<MemSidePort, &MemSidePort::processRequestEvent>
145 RequestEvent;
146
147 virtual void scheduleRequestEvent(Tick t) {
148 new RequestEvent(this, t);
149 }
126 typedef EventWrapper<MemSidePort, &MemSidePort::processSendEvent>
127 SendEvent;
150 };
151
152 /** Tag and data Storage */
153 TagStore *tags;
128 };
129
130 /** Tag and data Storage */
131 TagStore *tags;
154 /** Miss and Writeback handler */
155 MissBuffer *missQueue;
132
156 /** Coherence protocol. */
157 Coherence *coherence;
158
159 /** Prefetcher */
160 BasePrefetcher *prefetcher;
161
162 /**
163 * The clock ratio of the outgoing bus.

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171 */
172 int busWidth;
173
174 /**
175 * The latency of a hit in this device.
176 */
177 int hitLatency;
178
133 /** Coherence protocol. */
134 Coherence *coherence;
135
136 /** Prefetcher */
137 BasePrefetcher *prefetcher;
138
139 /**
140 * The clock ratio of the outgoing bus.

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148 */
149 int busWidth;
150
151 /**
152 * The latency of a hit in this device.
153 */
154 int hitLatency;
155
179 /**
180 * A permanent mem req to always be used to cause invalidations.
181 * Used to append to target list, to cause an invalidation.
182 */
183 PacketPtr invalidatePkt;
184 Request *invalidateReq;
185
186 /**
156 /**
187 * Policy class for performing compression.
188 */
189 CompressionAlgorithm *compressionAlg;
190
191 /**
192 * The block size of this cache. Set to value in the Tags object.
193 */
194 const int16_t blkSize;
195
196 /**
197 * Can this cache should allocate a block on a line-sized write miss.
198 */
199 const bool doFastWrites;
200
201 const bool prefetchMiss;
202
203 /**
157 * Can this cache should allocate a block on a line-sized write miss.
158 */
159 const bool doFastWrites;
160
161 const bool prefetchMiss;
162
163 /**
204 * Can the data can be stored in a compressed form.
205 */
206 const bool storeCompressed;
207
208 /**
209 * Do we need to compress blocks on writebacks (i.e. because
210 * writeback bus is compressed but storage is not)?
211 */
212 const bool compressOnWriteback;
213
214 /**
215 * The latency of a compression operation.
216 */
217 const int16_t compLatency;
218
219 /**
220 * Should we use an adaptive compression scheme.
221 */
222 const bool adaptiveCompression;
223
224 /**
225 * Do writebacks need to be compressed (i.e. because writeback bus
226 * is compressed), whether or not they're already compressed for
227 * storage.
228 */
229 const bool writebackCompressed;
230
231 /**
232 * Compare the internal block data to the fast access block data.
233 * @param blk The cache block to check.
234 * @return True if the data is the same.
235 */
236 bool verifyData(BlkType *blk);
237
238 /**
239 * Update the internal data of the block. The data to write is assumed to
240 * be in the fast access data.
241 * @param blk The block with the data to update.
242 * @param writebacks A list to store any generated writebacks.
243 * @param compress_block True if we should compress this block
244 */
245 void updateData(BlkType *blk, PacketList &writebacks, bool compress_block);
246
247 /**
248 * Handle a replacement for the given request.
249 * @param blk A pointer to the block, usually NULL
250 * @param pkt The memory request to satisfy.
251 * @param new_state The new state of the block.
252 * @param writebacks A list to store any generated writebacks.
253 */
164 * Handle a replacement for the given request.
165 * @param blk A pointer to the block, usually NULL
166 * @param pkt The memory request to satisfy.
167 * @param new_state The new state of the block.
168 * @param writebacks A list to store any generated writebacks.
169 */
254 BlkType* doReplacement(BlkType *blk, PacketPtr &pkt,
170 BlkType* doReplacement(BlkType *blk, PacketPtr pkt,
255 CacheBlk::State new_state, PacketList &writebacks);
256
257 /**
258 * Does all the processing necessary to perform the provided request.
259 * @param pkt The memory request to perform.
260 * @param lat The latency of the access.
261 * @param writebacks List for any writebacks that need to be performed.
262 * @param update True if the replacement data should be updated.
263 * @return Pointer to the cache block touched by the request. NULL if it
264 * was a miss.
265 */
171 CacheBlk::State new_state, PacketList &writebacks);
172
173 /**
174 * Does all the processing necessary to perform the provided request.
175 * @param pkt The memory request to perform.
176 * @param lat The latency of the access.
177 * @param writebacks List for any writebacks that need to be performed.
178 * @param update True if the replacement data should be updated.
179 * @return Pointer to the cache block touched by the request. NULL if it
180 * was a miss.
181 */
266 BlkType* handleAccess(PacketPtr &pkt, int & lat,
267 PacketList & writebacks, bool update = true);
182 bool access(PacketPtr pkt, BlkType *blk, int & lat);
268
183
269
270 /**
271 *Handle doing the Compare and Swap function for SPARC.
272 */
184 /**
185 *Handle doing the Compare and Swap function for SPARC.
186 */
273 void cmpAndSwap(BlkType *blk, PacketPtr &pkt);
187 void cmpAndSwap(BlkType *blk, PacketPtr pkt);
274
275 /**
276 * Populates a cache block and handles all outstanding requests for the
188
189 /**
190 * Populates a cache block and handles all outstanding requests for the
277 * satisfied fill request. This version takes an MSHR pointer and uses its
278 * request to fill the cache block, while repsonding to its targets.
279 * @param blk The cache block if it already exists.
280 * @param mshr The MSHR that contains the fill data and targets to satisfy.
281 * @param new_state The state of the new cache block.
282 * @param writebacks List for any writebacks that need to be performed.
283 * @return Pointer to the new cache block.
284 */
285 BlkType* handleFill(BlkType *blk, MSHR * mshr, CacheBlk::State new_state,
286 PacketList & writebacks, PacketPtr pkt);
287
288 /**
289 * Populates a cache block and handles all outstanding requests for the
290 * satisfied fill request. This version takes two memory requests. One
291 * contains the fill data, the other is an optional target to satisfy.
292 * Used for Cache::probe.
191 * satisfied fill request. This version takes two memory requests. One
192 * contains the fill data, the other is an optional target to satisfy.
193 * Used for Cache::probe.
293 * @param blk The cache block if it already exists.
294 * @param pkt The memory request with the fill data.
194 * @param pkt The memory request with the fill data.
295 * @param new_state The state of the new cache block.
195 * @param blk The cache block if it already exists.
296 * @param writebacks List for any writebacks that need to be performed.
196 * @param writebacks List for any writebacks that need to be performed.
297 * @param target The memory request to perform after the fill.
298 * @return Pointer to the new cache block.
299 */
197 * @return Pointer to the new cache block.
198 */
300 BlkType* handleFill(BlkType *blk, PacketPtr &pkt,
301 CacheBlk::State new_state,
302 PacketList & writebacks, PacketPtr target = NULL);
199 BlkType *handleFill(PacketPtr pkt, BlkType *blk,
200 PacketList &writebacks);
303
201
304 /**
305 * Sets the blk to the new state and handles the given request.
306 * @param blk The cache block being snooped.
307 * @param new_state The new coherence state for the block.
308 * @param pkt The request to satisfy
309 */
310 void handleSnoop(BlkType *blk, CacheBlk::State new_state,
311 PacketPtr &pkt);
202 bool satisfyCpuSideRequest(PacketPtr pkt, BlkType *blk);
203 bool satisfyTarget(MSHR::Target *target, BlkType *blk);
204 void satisfyMSHR(MSHR *mshr, PacketPtr pkt, BlkType *blk);
312
205
206 void doTimingSupplyResponse(PacketPtr req_pkt, uint8_t *blk_data);
207
313 /**
314 * Sets the blk to the new state.
315 * @param blk The cache block being snooped.
316 * @param new_state The new coherence state for the block.
317 */
208 /**
209 * Sets the blk to the new state.
210 * @param blk The cache block being snooped.
211 * @param new_state The new coherence state for the block.
212 */
318 void handleSnoop(BlkType *blk, CacheBlk::State new_state);
213 void handleSnoop(PacketPtr ptk, BlkType *blk, bool is_timing);
319
320 /**
321 * Create a writeback request for the given block.
322 * @param blk The block to writeback.
323 * @return The writeback request for the block.
324 */
325 PacketPtr writebackBlk(BlkType *blk);
326
327 public:
328
329 class Params
330 {
331 public:
332 TagStore *tags;
214
215 /**
216 * Create a writeback request for the given block.
217 * @param blk The block to writeback.
218 * @return The writeback request for the block.
219 */
220 PacketPtr writebackBlk(BlkType *blk);
221
222 public:
223
224 class Params
225 {
226 public:
227 TagStore *tags;
333 MissBuffer *missQueue;
334 Coherence *coherence;
335 BaseCache::Params baseParams;
336 BasePrefetcher*prefetcher;
337 bool prefetchAccess;
228 Coherence *coherence;
229 BaseCache::Params baseParams;
230 BasePrefetcher*prefetcher;
231 bool prefetchAccess;
338 int hitLatency;
339 CompressionAlgorithm *compressionAlg;
340 const int16_t blkSize;
341 const bool doFastWrites;
342 const bool prefetchMiss;
232 const bool doFastWrites;
233 const bool prefetchMiss;
343 const bool storeCompressed;
344 const bool compressOnWriteback;
345 const int16_t compLatency;
346 const bool adaptiveCompression;
347 const bool writebackCompressed;
348
234
349 Params(TagStore *_tags, MissBuffer *mq, Coherence *coh,
235 Params(TagStore *_tags, Coherence *coh,
350 BaseCache::Params params,
351 BasePrefetcher *_prefetcher,
352 bool prefetch_access, int hit_latency,
353 bool do_fast_writes,
236 BaseCache::Params params,
237 BasePrefetcher *_prefetcher,
238 bool prefetch_access, int hit_latency,
239 bool do_fast_writes,
354 bool store_compressed, bool adaptive_compression,
355 bool writeback_compressed,
356 CompressionAlgorithm *_compressionAlg, int comp_latency,
357 bool prefetch_miss)
240 bool prefetch_miss)
358 : tags(_tags), missQueue(mq), coherence(coh),
241 : tags(_tags), coherence(coh),
359 baseParams(params),
360 prefetcher(_prefetcher), prefetchAccess(prefetch_access),
242 baseParams(params),
243 prefetcher(_prefetcher), prefetchAccess(prefetch_access),
361 hitLatency(hit_latency),
362 compressionAlg(_compressionAlg),
363 blkSize(_tags->getBlockSize()),
364 doFastWrites(do_fast_writes),
244 doFastWrites(do_fast_writes),
365 prefetchMiss(prefetch_miss),
366 storeCompressed(store_compressed),
367 compressOnWriteback(!store_compressed && writeback_compressed),
368 compLatency(comp_latency),
369 adaptiveCompression(adaptive_compression),
370 writebackCompressed(writeback_compressed)
245 prefetchMiss(prefetch_miss)
371 {
372 }
373 };
374
375 /** Instantiates a basic cache object. */
376 Cache(const std::string &_name, Params &params);
377
378 virtual Port *getPort(const std::string &if_name, int idx = -1);
379 virtual void deletePortRefs(Port *p);
380
381 void regStats();
382
383 /**
384 * Performs the access specified by the request.
385 * @param pkt The request to perform.
386 * @return The result of the access.
387 */
246 {
247 }
248 };
249
250 /** Instantiates a basic cache object. */
251 Cache(const std::string &_name, Params &params);
252
253 virtual Port *getPort(const std::string &if_name, int idx = -1);
254 virtual void deletePortRefs(Port *p);
255
256 void regStats();
257
258 /**
259 * Performs the access specified by the request.
260 * @param pkt The request to perform.
261 * @return The result of the access.
262 */
388 bool access(PacketPtr &pkt);
263 bool timingAccess(PacketPtr pkt);
389
390 /**
264
265 /**
391 * Selects a request to send on the bus.
392 * @return The memory request to service.
266 * Performs the access specified by the request.
267 * @param pkt The request to perform.
268 * @return The result of the access.
393 */
269 */
394 PacketPtr getPacket();
270 Tick atomicAccess(PacketPtr pkt);
395
396 /**
271
272 /**
397 * Was the request was sent successfully?
398 * @param pkt The request.
399 * @param success True if the request was sent successfully.
273 * Performs the access specified by the request.
274 * @param pkt The request to perform.
275 * @return The result of the access.
400 */
276 */
401 void sendResult(PacketPtr &pkt, MSHR* mshr, bool success);
277 void functionalAccess(PacketPtr pkt, CachePort *otherSidePort);
402
403 /**
404 * Handles a response (cache line fill/write ack) from the bus.
405 * @param pkt The request being responded to.
406 */
278
279 /**
280 * Handles a response (cache line fill/write ack) from the bus.
281 * @param pkt The request being responded to.
282 */
407 void handleResponse(PacketPtr &pkt);
283 void handleResponse(PacketPtr pkt);
408
409 /**
410 * Snoops bus transactions to maintain coherence.
411 * @param pkt The current bus transaction.
412 */
284
285 /**
286 * Snoops bus transactions to maintain coherence.
287 * @param pkt The current bus transaction.
288 */
413 void snoop(PacketPtr &pkt);
289 void snoopTiming(PacketPtr pkt);
414
290
415 void snoopResponse(PacketPtr &pkt);
291 /**
292 * Snoop for the provided request in the cache and return the estimated
293 * time of completion.
294 * @param pkt The memory request to snoop
295 * @return The estimated completion time.
296 */
297 Tick snoopAtomic(PacketPtr pkt);
416
417 /**
418 * Squash all requests associated with specified thread.
419 * intended for use by I-cache.
420 * @param threadNum The thread to squash.
421 */
298
299 /**
300 * Squash all requests associated with specified thread.
301 * intended for use by I-cache.
302 * @param threadNum The thread to squash.
303 */
422 void squash(int threadNum)
423 {
424 missQueue->squash(threadNum);
425 }
304 void squash(int threadNum);
426
427 /**
305
306 /**
428 * Return the number of outstanding misses in a Cache.
429 * Default returns 0.
430 *
431 * @retval unsigned The number of missing still outstanding.
307 * Allocate a new MSHR or write buffer to handle a miss.
308 * @param pkt The access that missed.
309 * @param time The time to continue processing the miss.
310 * @param isFill Whether to fetch & allocate a block
311 * or just forward the request.
432 */
312 */
433 unsigned outstandingMisses() const
434 {
435 return missQueue->getMisses();
436 }
313 MSHR *allocateBuffer(PacketPtr pkt, Tick time, bool isFill,
314 bool requestBus);
437
438 /**
315
316 /**
439 * Perform the access specified in the request and return the estimated
440 * time of completion. This function can either update the hierarchy state
441 * or just perform the access wherever the data is found depending on the
442 * state of the update flag.
443 * @param pkt The memory request to satisfy
444 * @param update If true, update the hierarchy, otherwise just perform the
445 * request.
446 * @return The estimated completion time.
317 * Selects a outstanding request to service.
318 * @return The request to service, NULL if none found.
447 */
319 */
448 Tick probe(PacketPtr &pkt, bool update, CachePort * otherSidePort);
320 MSHR *getNextMSHR();
321 PacketPtr getPacket();
449
450 /**
322
323 /**
451 * Snoop for the provided request in the cache and return the estimated
452 * time of completion.
453 * @todo Can a snoop probe not change state?
454 * @param pkt The memory request to satisfy
455 * @param update If true, update the hierarchy, otherwise just perform the
456 * request.
457 * @return The estimated completion time.
324 * Marks a request as in service (sent on the bus). This can have side
325 * effect since storage for no response commands is deallocated once they
326 * are successfully sent.
327 * @param pkt The request that was sent on the bus.
458 */
328 */
459 Tick snoopProbe(PacketPtr &pkt);
329 void markInService(MSHR *mshr);
460
330
331 /**
332 * Collect statistics and free resources of a satisfied request.
333 * @param pkt The request that has been satisfied.
334 * @param time The time when the request is satisfied.
335 */
336 void handleResponse(PacketPtr pkt, Tick time);
337
338 /**
339 * Perform the given writeback request.
340 * @param pkt The writeback request.
341 */
342 void doWriteback(PacketPtr pkt);
343
344 /**
345 * Return whether there are any outstanding misses.
346 */
347 bool outstandingMisses() const
348 {
349 return mshrQueue.allocated != 0;
350 }
351
352 CacheBlk *findBlock(Addr addr) {
353 return tags->findBlock(addr);
354 }
355
461 bool inCache(Addr addr) {
462 return (tags->findBlock(addr) != 0);
463 }
464
465 bool inMissQueue(Addr addr) {
356 bool inCache(Addr addr) {
357 return (tags->findBlock(addr) != 0);
358 }
359
360 bool inMissQueue(Addr addr) {
466 return (missQueue->findMSHR(addr) != 0);
361 return (mshrQueue.findMatch(addr) != 0);
467 }
468};
469
470#endif // __CACHE_HH__
362 }
363};
364
365#endif // __CACHE_HH__