cache.hh (4219:e3f636da1042) cache.hh (4458:d43aab911e6e)
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Erik Hallnor
29 * Dave Greene
30 * Steve Reinhardt
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Erik Hallnor
29 * Dave Greene
30 * Steve Reinhardt
31 * Ron Dreslinski
31 */
32
33/**
34 * @file
35 * Describes a cache based on template policies.
36 */
37
38#ifndef __CACHE_HH__
39#define __CACHE_HH__
40
41#include "base/compression/base.hh"
42#include "base/misc.hh" // fatal, panic, and warn
43#include "cpu/smt.hh" // SMT_MAX_THREADS
44
45#include "mem/cache/base_cache.hh"
46#include "mem/cache/cache_blk.hh"
47#include "mem/cache/miss/miss_buffer.hh"
48
32 */
33
34/**
35 * @file
36 * Describes a cache based on template policies.
37 */
38
39#ifndef __CACHE_HH__
40#define __CACHE_HH__
41
42#include "base/compression/base.hh"
43#include "base/misc.hh" // fatal, panic, and warn
44#include "cpu/smt.hh" // SMT_MAX_THREADS
45
46#include "mem/cache/base_cache.hh"
47#include "mem/cache/cache_blk.hh"
48#include "mem/cache/miss/miss_buffer.hh"
49
50#include "sim/eventq.hh"
51
49//Forward decleration
50class MSHR;
51class BasePrefetcher;
52
53/**
54 * A template-policy based cache. The behavior of the cache can be altered by
55 * supplying different template policies. TagStore handles all tag and data
56 * storage @sa TagStore. Buffering handles all misses and writes/writebacks

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78
79 // BaseCache::CachePort just has a BaseCache *; this function
80 // lets us get back the type info we lost when we stored the
81 // cache pointer there.
82 Cache<TagStore,Coherence> *myCache() {
83 return static_cast<Cache<TagStore,Coherence> *>(cache);
84 }
85
52//Forward decleration
53class MSHR;
54class BasePrefetcher;
55
56/**
57 * A template-policy based cache. The behavior of the cache can be altered by
58 * supplying different template policies. TagStore handles all tag and data
59 * storage @sa TagStore. Buffering handles all misses and writes/writebacks

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81
82 // BaseCache::CachePort just has a BaseCache *; this function
83 // lets us get back the type info we lost when we stored the
84 // cache pointer there.
85 Cache<TagStore,Coherence> *myCache() {
86 return static_cast<Cache<TagStore,Coherence> *>(cache);
87 }
88
89 void processRequestEvent();
90 void processResponseEvent();
91
86 virtual bool recvTiming(PacketPtr pkt);
87
92 virtual bool recvTiming(PacketPtr pkt);
93
94 virtual void recvRetry();
95
88 virtual Tick recvAtomic(PacketPtr pkt);
89
90 virtual void recvFunctional(PacketPtr pkt);
96 virtual Tick recvAtomic(PacketPtr pkt);
97
98 virtual void recvFunctional(PacketPtr pkt);
99
100 typedef EventWrapper<CpuSidePort, &CpuSidePort::processResponseEvent>
101 ResponseEvent;
102
103 typedef EventWrapper<CpuSidePort, &CpuSidePort::processRequestEvent>
104 RequestEvent;
105
106 virtual void scheduleRequestEvent(Tick t) {
107 new RequestEvent(this, t);
108 }
91 };
92
93 class MemSidePort : public CachePort
94 {
95 public:
96 MemSidePort(const std::string &_name,
97 Cache<TagStore,Coherence> *_cache);
98
99 // BaseCache::CachePort just has a BaseCache *; this function
100 // lets us get back the type info we lost when we stored the
101 // cache pointer there.
102 Cache<TagStore,Coherence> *myCache() {
103 return static_cast<Cache<TagStore,Coherence> *>(cache);
104 }
105
109 };
110
111 class MemSidePort : public CachePort
112 {
113 public:
114 MemSidePort(const std::string &_name,
115 Cache<TagStore,Coherence> *_cache);
116
117 // BaseCache::CachePort just has a BaseCache *; this function
118 // lets us get back the type info we lost when we stored the
119 // cache pointer there.
120 Cache<TagStore,Coherence> *myCache() {
121 return static_cast<Cache<TagStore,Coherence> *>(cache);
122 }
123
124 void processRequestEvent();
125 void processResponseEvent();
126
106 virtual bool recvTiming(PacketPtr pkt);
107
127 virtual bool recvTiming(PacketPtr pkt);
128
129 virtual void recvRetry();
130
108 virtual Tick recvAtomic(PacketPtr pkt);
109
110 virtual void recvFunctional(PacketPtr pkt);
131 virtual Tick recvAtomic(PacketPtr pkt);
132
133 virtual void recvFunctional(PacketPtr pkt);
134
135 typedef EventWrapper<MemSidePort, &MemSidePort::processResponseEvent>
136 ResponseEvent;
137
138 typedef EventWrapper<MemSidePort, &MemSidePort::processRequestEvent>
139 RequestEvent;
140
141 virtual void scheduleRequestEvent(Tick t) {
142 new RequestEvent(this, t);
143 }
111 };
112
113 /** Tag and data Storage */
114 TagStore *tags;
115 /** Miss and Writeback handler */
116 MissBuffer *missQueue;
117 /** Coherence protocol. */
118 Coherence *coherence;

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334 };
335
336 /** Instantiates a basic cache object. */
337 Cache(const std::string &_name, Params &params);
338
339 virtual Port *getPort(const std::string &if_name, int idx = -1);
340 virtual void deletePortRefs(Port *p);
341
144 };
145
146 /** Tag and data Storage */
147 TagStore *tags;
148 /** Miss and Writeback handler */
149 MissBuffer *missQueue;
150 /** Coherence protocol. */
151 Coherence *coherence;

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367 };
368
369 /** Instantiates a basic cache object. */
370 Cache(const std::string &_name, Params &params);
371
372 virtual Port *getPort(const std::string &if_name, int idx = -1);
373 virtual void deletePortRefs(Port *p);
374
342 virtual void recvStatusChange(Port::Status status, bool isCpuSide);
343
344 void regStats();
345
346 /**
347 * Performs the access specified by the request.
348 * @param pkt The request to perform.
349 * @return The result of the access.
350 */
351 bool access(PacketPtr &pkt);
352
353 /**
354 * Selects a request to send on the bus.
355 * @return The memory request to service.
356 */
375 void regStats();
376
377 /**
378 * Performs the access specified by the request.
379 * @param pkt The request to perform.
380 * @return The result of the access.
381 */
382 bool access(PacketPtr &pkt);
383
384 /**
385 * Selects a request to send on the bus.
386 * @return The memory request to service.
387 */
357 virtual PacketPtr getPacket();
388 PacketPtr getPacket();
358
359 /**
360 * Was the request was sent successfully?
361 * @param pkt The request.
362 * @param success True if the request was sent successfully.
363 */
389
390 /**
391 * Was the request was sent successfully?
392 * @param pkt The request.
393 * @param success True if the request was sent successfully.
394 */
364 virtual void sendResult(PacketPtr &pkt, MSHR* mshr, bool success);
395 void sendResult(PacketPtr &pkt, MSHR* mshr, bool success);
365
366 /**
396
397 /**
367 * Was the CSHR request was sent successfully?
368 * @param pkt The request.
369 * @param success True if the request was sent successfully.
370 */
371 virtual void sendCoherenceResult(PacketPtr &pkt, MSHR* cshr, bool success);
372
373 /**
374 * Handles a response (cache line fill/write ack) from the bus.
375 * @param pkt The request being responded to.
376 */
377 void handleResponse(PacketPtr &pkt);
378
379 /**
398 * Handles a response (cache line fill/write ack) from the bus.
399 * @param pkt The request being responded to.
400 */
401 void handleResponse(PacketPtr &pkt);
402
403 /**
380 * Selects a coherence message to forward to lower levels of the hierarchy.
381 * @return The coherence message to forward.
382 */
383 virtual PacketPtr getCoherencePacket();
384
385 /**
386 * Snoops bus transactions to maintain coherence.
387 * @param pkt The current bus transaction.
388 */
389 void snoop(PacketPtr &pkt);
390
391 void snoopResponse(PacketPtr &pkt);
392
393 /**

--- 53 unchanged lines hidden --- 		404 * Snoops bus transactions to maintain coherence.
405 * @param pkt The current bus transaction.
406 */
407 void snoop(PacketPtr &pkt);
408
409 void snoopResponse(PacketPtr &pkt);
410
411 /**

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