cache.hh (3860:73e3642713a3) cache.hh (3861:3b35b0f0b6a9)
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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40
41#include "base/compression/base.hh"
42#include "base/misc.hh" // fatal, panic, and warn
43#include "cpu/smt.hh" // SMT_MAX_THREADS
44
45#include "mem/cache/base_cache.hh"
46#include "mem/cache/cache_blk.hh"
47#include "mem/cache/miss/miss_buffer.hh"
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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40
41#include "base/compression/base.hh"
42#include "base/misc.hh" // fatal, panic, and warn
43#include "cpu/smt.hh" // SMT_MAX_THREADS
44
45#include "mem/cache/base_cache.hh"
46#include "mem/cache/cache_blk.hh"
47#include "mem/cache/miss/miss_buffer.hh"
48#include "mem/cache/prefetch/prefetcher.hh"
49
50//Forward decleration
51class MSHR;
48
49//Forward decleration
50class MSHR;
51class BasePrefetcher;
52
52
53
54/**
55 * A template-policy based cache. The behavior of the cache can be altered by
56 * supplying different template policies. TagStore handles all tag and data
57 * storage @sa TagStore. Buffering handles all misses and writes/writebacks
58 * @sa MissQueue. Coherence handles all coherence policy details @sa
59 * UniCoherence, SimpleMultiCoherence.
60 */
61template <class TagStore, class Coherence>

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114 /** Tag and data Storage */
115 TagStore *tags;
116 /** Miss and Writeback handler */
117 MissBuffer *missQueue;
118 /** Coherence protocol. */
119 Coherence *coherence;
120
121 /** Prefetcher */
53/**
54 * A template-policy based cache. The behavior of the cache can be altered by
55 * supplying different template policies. TagStore handles all tag and data
56 * storage @sa TagStore. Buffering handles all misses and writes/writebacks
57 * @sa MissQueue. Coherence handles all coherence policy details @sa
58 * UniCoherence, SimpleMultiCoherence.
59 */
60template <class TagStore, class Coherence>

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113 /** Tag and data Storage */
114 TagStore *tags;
115 /** Miss and Writeback handler */
116 MissBuffer *missQueue;
117 /** Coherence protocol. */
118 Coherence *coherence;
119
120 /** Prefetcher */
122 Prefetcher<TagStore> *prefetcher;
121 BasePrefetcher *prefetcher;
123
124 /**
125 * The clock ratio of the outgoing bus.
126 * Used for calculating critical word first.
127 */
128 int busRatio;
129
130 /**

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299
300 class Params
301 {
302 public:
303 TagStore *tags;
304 MissBuffer *missQueue;
305 Coherence *coherence;
306 BaseCache::Params baseParams;
122
123 /**
124 * The clock ratio of the outgoing bus.
125 * Used for calculating critical word first.
126 */
127 int busRatio;
128
129 /**

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298
299 class Params
300 {
301 public:
302 TagStore *tags;
303 MissBuffer *missQueue;
304 Coherence *coherence;
305 BaseCache::Params baseParams;
307 Prefetcher<TagStore> *prefetcher;
306 BasePrefetcher*prefetcher;
308 bool prefetchAccess;
309 int hitLatency;
310 CompressionAlgorithm *compressionAlg;
311 const int16_t blkSize;
312 const bool doFastWrites;
313 const bool prefetchMiss;
314 const bool storeCompressed;
315 const bool compressOnWriteback;
316 const int16_t compLatency;
317 const bool adaptiveCompression;
318 const bool writebackCompressed;
319
320 Params(TagStore *_tags, MissBuffer *mq, Coherence *coh,
321 BaseCache::Params params,
307 bool prefetchAccess;
308 int hitLatency;
309 CompressionAlgorithm *compressionAlg;
310 const int16_t blkSize;
311 const bool doFastWrites;
312 const bool prefetchMiss;
313 const bool storeCompressed;
314 const bool compressOnWriteback;
315 const int16_t compLatency;
316 const bool adaptiveCompression;
317 const bool writebackCompressed;
318
319 Params(TagStore *_tags, MissBuffer *mq, Coherence *coh,
320 BaseCache::Params params,
322 Prefetcher<TagStore> *_prefetcher,
321 BasePrefetcher *_prefetcher,
323 bool prefetch_access, int hit_latency,
324 bool do_fast_writes,
325 bool store_compressed, bool adaptive_compression,
326 bool writeback_compressed,
327 CompressionAlgorithm *_compressionAlg, int comp_latency,
328 bool prefetch_miss)
329 : tags(_tags), missQueue(mq), coherence(coh),
330 baseParams(params),

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445 * time of completion.
446 * @todo Can a snoop probe not change state?
447 * @param pkt The memory request to satisfy
448 * @param update If true, update the hierarchy, otherwise just perform the
449 * request.
450 * @return The estimated completion time.
451 */
452 Tick snoopProbe(PacketPtr &pkt);
322 bool prefetch_access, int hit_latency,
323 bool do_fast_writes,
324 bool store_compressed, bool adaptive_compression,
325 bool writeback_compressed,
326 CompressionAlgorithm *_compressionAlg, int comp_latency,
327 bool prefetch_miss)
328 : tags(_tags), missQueue(mq), coherence(coh),
329 baseParams(params),

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444 * time of completion.
445 * @todo Can a snoop probe not change state?
446 * @param pkt The memory request to satisfy
447 * @param update If true, update the hierarchy, otherwise just perform the
448 * request.
449 * @return The estimated completion time.
450 */
451 Tick snoopProbe(PacketPtr &pkt);
452
453 bool inCache(Addr addr) {
454 return (tags->findBlock(addr) != 0);
455 }
456
457 bool inMissQueue(Addr addr) {
458 return (missQueue->findMSHR(addr) != 0);
459 }
453};
454
455#endif // __CACHE_HH__
460};
461
462#endif // __CACHE_HH__