cache.hh (3738:c06cd072bbbe) cache.hh (3860:73e3642713a3)
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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33/**
34 * @file
35 * Describes a cache based on template policies.
36 */
37
38#ifndef __CACHE_HH__
39#define __CACHE_HH__
40
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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33/**
34 * @file
35 * Describes a cache based on template policies.
36 */
37
38#ifndef __CACHE_HH__
39#define __CACHE_HH__
40
41#include "base/compression/base.hh"
41#include "base/misc.hh" // fatal, panic, and warn
42#include "cpu/smt.hh" // SMT_MAX_THREADS
43
44#include "mem/cache/base_cache.hh"
42#include "base/misc.hh" // fatal, panic, and warn
43#include "cpu/smt.hh" // SMT_MAX_THREADS
44
45#include "mem/cache/base_cache.hh"
46#include "mem/cache/cache_blk.hh"
45#include "mem/cache/miss/miss_buffer.hh"
46#include "mem/cache/prefetch/prefetcher.hh"
47
48//Forward decleration
49class MSHR;
50
51
52/**

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57 * UniCoherence, SimpleMultiCoherence.
58 */
59template <class TagStore, class Coherence>
60class Cache : public BaseCache
61{
62 public:
63 /** Define the type of cache block to use. */
64 typedef typename TagStore::BlkType BlkType;
47#include "mem/cache/miss/miss_buffer.hh"
48#include "mem/cache/prefetch/prefetcher.hh"
49
50//Forward decleration
51class MSHR;
52
53
54/**

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59 * UniCoherence, SimpleMultiCoherence.
60 */
61template <class TagStore, class Coherence>
62class Cache : public BaseCache
63{
64 public:
65 /** Define the type of cache block to use. */
66 typedef typename TagStore::BlkType BlkType;
67 /** A typedef for a list of BlkType pointers. */
68 typedef typename TagStore::BlkList BlkList;
65
66 bool prefetchAccess;
67
68 protected:
69
70 class CpuSidePort : public CachePort
71 {
72 public:

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136
137 /**
138 * A permanent mem req to always be used to cause invalidations.
139 * Used to append to target list, to cause an invalidation.
140 */
141 PacketPtr invalidatePkt;
142 Request *invalidateReq;
143
69
70 bool prefetchAccess;
71
72 protected:
73
74 class CpuSidePort : public CachePort
75 {
76 public:

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140
141 /**
142 * A permanent mem req to always be used to cause invalidations.
143 * Used to append to target list, to cause an invalidation.
144 */
145 PacketPtr invalidatePkt;
146 Request *invalidateReq;
147
148 /**
149 * Policy class for performing compression.
150 */
151 CompressionAlgorithm *compressionAlg;
152
153 /**
154 * The block size of this cache. Set to value in the Tags object.
155 */
156 const int16_t blkSize;
157
158 /**
159 * Can this cache should allocate a block on a line-sized write miss.
160 */
161 const bool doFastWrites;
162
163 const bool prefetchMiss;
164
165 /**
166 * Can the data can be stored in a compressed form.
167 */
168 const bool storeCompressed;
169
170 /**
171 * Do we need to compress blocks on writebacks (i.e. because
172 * writeback bus is compressed but storage is not)?
173 */
174 const bool compressOnWriteback;
175
176 /**
177 * The latency of a compression operation.
178 */
179 const int16_t compLatency;
180
181 /**
182 * Should we use an adaptive compression scheme.
183 */
184 const bool adaptiveCompression;
185
186 /**
187 * Do writebacks need to be compressed (i.e. because writeback bus
188 * is compressed), whether or not they're already compressed for
189 * storage.
190 */
191 const bool writebackCompressed;
192
193 /**
194 * Compare the internal block data to the fast access block data.
195 * @param blk The cache block to check.
196 * @return True if the data is the same.
197 */
198 bool verifyData(BlkType *blk);
199
200 /**
201 * Update the internal data of the block. The data to write is assumed to
202 * be in the fast access data.
203 * @param blk The block with the data to update.
204 * @param writebacks A list to store any generated writebacks.
205 * @param compress_block True if we should compress this block
206 */
207 void updateData(BlkType *blk, PacketList &writebacks, bool compress_block);
208
209 /**
210 * Handle a replacement for the given request.
211 * @param blk A pointer to the block, usually NULL
212 * @param pkt The memory request to satisfy.
213 * @param new_state The new state of the block.
214 * @param writebacks A list to store any generated writebacks.
215 */
216 BlkType* doReplacement(BlkType *blk, PacketPtr &pkt,
217 CacheBlk::State new_state, PacketList &writebacks);
218
219 /**
220 * Does all the processing necessary to perform the provided request.
221 * @param pkt The memory request to perform.
222 * @param lat The latency of the access.
223 * @param writebacks List for any writebacks that need to be performed.
224 * @param update True if the replacement data should be updated.
225 * @return Pointer to the cache block touched by the request. NULL if it
226 * was a miss.
227 */
228 BlkType* handleAccess(PacketPtr &pkt, int & lat,
229 PacketList & writebacks, bool update = true);
230
231 /**
232 * Populates a cache block and handles all outstanding requests for the
233 * satisfied fill request. This version takes an MSHR pointer and uses its
234 * request to fill the cache block, while repsonding to its targets.
235 * @param blk The cache block if it already exists.
236 * @param mshr The MSHR that contains the fill data and targets to satisfy.
237 * @param new_state The state of the new cache block.
238 * @param writebacks List for any writebacks that need to be performed.
239 * @return Pointer to the new cache block.
240 */
241 BlkType* handleFill(BlkType *blk, MSHR * mshr, CacheBlk::State new_state,
242 PacketList & writebacks, PacketPtr pkt);
243
244 /**
245 * Populates a cache block and handles all outstanding requests for the
246 * satisfied fill request. This version takes two memory requests. One
247 * contains the fill data, the other is an optional target to satisfy.
248 * Used for Cache::probe.
249 * @param blk The cache block if it already exists.
250 * @param pkt The memory request with the fill data.
251 * @param new_state The state of the new cache block.
252 * @param writebacks List for any writebacks that need to be performed.
253 * @param target The memory request to perform after the fill.
254 * @return Pointer to the new cache block.
255 */
256 BlkType* handleFill(BlkType *blk, PacketPtr &pkt,
257 CacheBlk::State new_state,
258 PacketList & writebacks, PacketPtr target = NULL);
259
260 /**
261 * Sets the blk to the new state and handles the given request.
262 * @param blk The cache block being snooped.
263 * @param new_state The new coherence state for the block.
264 * @param pkt The request to satisfy
265 */
266 void handleSnoop(BlkType *blk, CacheBlk::State new_state,
267 PacketPtr &pkt);
268
269 /**
270 * Sets the blk to the new state.
271 * @param blk The cache block being snooped.
272 * @param new_state The new coherence state for the block.
273 */
274 void handleSnoop(BlkType *blk, CacheBlk::State new_state);
275
276 /**
277 * Create a writeback request for the given block.
278 * @param blk The block to writeback.
279 * @return The writeback request for the block.
280 */
281 PacketPtr writebackBlk(BlkType *blk);
282
283 BlkType* findBlock(Addr addr)
284 {
285 return tags->findBlock(addr);
286 }
287
288 BlkType* findBlock(PacketPtr &pkt)
289 {
290 return tags->findBlock(pkt->getAddr());
291 }
292
293 void invalidateBlk(CacheBlk *blk)
294 {
295 tags->invalidateBlk(tags->regenerateBlkAddr(blk->tag, blk->set));
296 }
297
144 public:
145
146 class Params
147 {
148 public:
149 TagStore *tags;
150 MissBuffer *missQueue;
151 Coherence *coherence;
152 BaseCache::Params baseParams;
153 Prefetcher<TagStore> *prefetcher;
154 bool prefetchAccess;
155 int hitLatency;
298 public:
299
300 class Params
301 {
302 public:
303 TagStore *tags;
304 MissBuffer *missQueue;
305 Coherence *coherence;
306 BaseCache::Params baseParams;
307 Prefetcher<TagStore> *prefetcher;
308 bool prefetchAccess;
309 int hitLatency;
310 CompressionAlgorithm *compressionAlg;
311 const int16_t blkSize;
312 const bool doFastWrites;
313 const bool prefetchMiss;
314 const bool storeCompressed;
315 const bool compressOnWriteback;
316 const int16_t compLatency;
317 const bool adaptiveCompression;
318 const bool writebackCompressed;
156
157 Params(TagStore *_tags, MissBuffer *mq, Coherence *coh,
158 BaseCache::Params params,
159 Prefetcher<TagStore> *_prefetcher,
319
320 Params(TagStore *_tags, MissBuffer *mq, Coherence *coh,
321 BaseCache::Params params,
322 Prefetcher<TagStore> *_prefetcher,
160 bool prefetch_access, int hit_latency)
323 bool prefetch_access, int hit_latency,
324 bool do_fast_writes,
325 bool store_compressed, bool adaptive_compression,
326 bool writeback_compressed,
327 CompressionAlgorithm *_compressionAlg, int comp_latency,
328 bool prefetch_miss)
161 : tags(_tags), missQueue(mq), coherence(coh),
162 baseParams(params),
163 prefetcher(_prefetcher), prefetchAccess(prefetch_access),
329 : tags(_tags), missQueue(mq), coherence(coh),
330 baseParams(params),
331 prefetcher(_prefetcher), prefetchAccess(prefetch_access),
164 hitLatency(hit_latency)
332 hitLatency(hit_latency),
333 compressionAlg(_compressionAlg),
334 blkSize(_tags->getBlockSize()),
335 doFastWrites(do_fast_writes),
336 prefetchMiss(prefetch_miss),
337 storeCompressed(store_compressed),
338 compressOnWriteback(!store_compressed && writeback_compressed),
339 compLatency(comp_latency),
340 adaptiveCompression(adaptive_compression),
341 writebackCompressed(writeback_compressed)
165 {
166 }
167 };
168
169 /** Instantiates a basic cache object. */
170 Cache(const std::string &_name, Params &params);
171
172 virtual Port *getPort(const std::string &if_name, int idx = -1);

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343 }
344 };
345
346 /** Instantiates a basic cache object. */
347 Cache(const std::string &_name, Params &params);
348
349 virtual Port *getPort(const std::string &if_name, int idx = -1);

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