cache.hh (3719:23ca579a363a) cache.hh (3738:c06cd072bbbe)
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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59template <class TagStore, class Coherence>
60class Cache : public BaseCache
61{
62 public:
63 /** Define the type of cache block to use. */
64 typedef typename TagStore::BlkType BlkType;
65
66 bool prefetchAccess;
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 50 unchanged lines hidden (view full) ---

59template <class TagStore, class Coherence>
60class Cache : public BaseCache
61{
62 public:
63 /** Define the type of cache block to use. */
64 typedef typename TagStore::BlkType BlkType;
65
66 bool prefetchAccess;
67
67 protected:
68
68 protected:
69
70 class CpuSidePort : public CachePort
71 {
72 public:
73 CpuSidePort(const std::string &_name,
74 Cache<TagStore,Coherence> *_cache);
75
76 // BaseCache::CachePort just has a BaseCache *; this function
77 // lets us get back the type info we lost when we stored the
78 // cache pointer there.
79 Cache<TagStore,Coherence> *myCache() {
80 return static_cast<Cache<TagStore,Coherence> *>(cache);
81 }
82
83 virtual bool recvTiming(PacketPtr pkt);
84
85 virtual Tick recvAtomic(PacketPtr pkt);
86
87 virtual void recvFunctional(PacketPtr pkt);
88 };
89
90 class MemSidePort : public CachePort
91 {
92 public:
93 MemSidePort(const std::string &_name,
94 Cache<TagStore,Coherence> *_cache);
95
96 // BaseCache::CachePort just has a BaseCache *; this function
97 // lets us get back the type info we lost when we stored the
98 // cache pointer there.
99 Cache<TagStore,Coherence> *myCache() {
100 return static_cast<Cache<TagStore,Coherence> *>(cache);
101 }
102
103 virtual bool recvTiming(PacketPtr pkt);
104
105 virtual Tick recvAtomic(PacketPtr pkt);
106
107 virtual void recvFunctional(PacketPtr pkt);
108 };
109
69 /** Tag and data Storage */
70 TagStore *tags;
71 /** Miss and Writeback handler */
72 MissBuffer *missQueue;
73 /** Coherence protocol. */
74 Coherence *coherence;
75
76 /** Prefetcher */

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123 hitLatency(hit_latency)
124 {
125 }
126 };
127
128 /** Instantiates a basic cache object. */
129 Cache(const std::string &_name, Params &params);
130
110 /** Tag and data Storage */
111 TagStore *tags;
112 /** Miss and Writeback handler */
113 MissBuffer *missQueue;
114 /** Coherence protocol. */
115 Coherence *coherence;
116
117 /** Prefetcher */

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164 hitLatency(hit_latency)
165 {
166 }
167 };
168
169 /** Instantiates a basic cache object. */
170 Cache(const std::string &_name, Params &params);
171
131 virtual bool doTimingAccess(PacketPtr pkt, CachePort *cachePort,
132 bool isCpuSide);
172 virtual Port *getPort(const std::string &if_name, int idx = -1);
133
173
134 virtual Tick doAtomicAccess(PacketPtr pkt, bool isCpuSide);
135
136 virtual void doFunctionalAccess(PacketPtr pkt, bool isCpuSide);
137
138 virtual void recvStatusChange(Port::Status status, bool isCpuSide);
139
140 void regStats();
141
142 /**
143 * Performs the access specified by the request.
144 * @param pkt The request to perform.
145 * @return The result of the access.

--- 97 unchanged lines hidden --- 		174 virtual void recvStatusChange(Port::Status status, bool isCpuSide);
175
176 void regStats();
177
178 /**
179 * Performs the access specified by the request.
180 * @param pkt The request to perform.
181 * @return The result of the access.

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