cache.hh (3349:fec4a86fa212) cache.hh (3719:23ca579a363a)
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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37
38#ifndef __CACHE_HH__
39#define __CACHE_HH__
40
41#include "base/misc.hh" // fatal, panic, and warn
42#include "cpu/smt.hh" // SMT_MAX_THREADS
43
44#include "mem/cache/base_cache.hh"
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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37
38#ifndef __CACHE_HH__
39#define __CACHE_HH__
40
41#include "base/misc.hh" // fatal, panic, and warn
42#include "cpu/smt.hh" // SMT_MAX_THREADS
43
44#include "mem/cache/base_cache.hh"
45#include "mem/cache/miss/miss_buffer.hh"
45#include "mem/cache/prefetch/prefetcher.hh"
46
47//Forward decleration
48class MSHR;
49
50
51/**
52 * A template-policy based cache. The behavior of the cache can be altered by
53 * supplying different template policies. TagStore handles all tag and data
54 * storage @sa TagStore. Buffering handles all misses and writes/writebacks
55 * @sa MissQueue. Coherence handles all coherence policy details @sa
56 * UniCoherence, SimpleMultiCoherence.
57 */
46#include "mem/cache/prefetch/prefetcher.hh"
47
48//Forward decleration
49class MSHR;
50
51
52/**
53 * A template-policy based cache. The behavior of the cache can be altered by
54 * supplying different template policies. TagStore handles all tag and data
55 * storage @sa TagStore. Buffering handles all misses and writes/writebacks
56 * @sa MissQueue. Coherence handles all coherence policy details @sa
57 * UniCoherence, SimpleMultiCoherence.
58 */
58template <class TagStore, class Buffering, class Coherence>
59template
59class Cache : public BaseCache
60{
61 public:
62 /** Define the type of cache block to use. */
63 typedef typename TagStore::BlkType BlkType;
64
65 bool prefetchAccess;
66 protected:
67
68 /** Tag and data Storage */
69 TagStore *tags;
70 /** Miss and Writeback handler */
60class Cache : public BaseCache
61{
62 public:
63 /** Define the type of cache block to use. */
64 typedef typename TagStore::BlkType BlkType;
65
66 bool prefetchAccess;
67 protected:
68
69 /** Tag and data Storage */
70 TagStore *tags;
71 /** Miss and Writeback handler */
71 Buffering *missQueue;
72 MissBuffer *missQueue;
72 /** Coherence protocol. */
73 Coherence *coherence;
74
75 /** Prefetcher */
73 /** Coherence protocol. */
74 Coherence *coherence;
75
76 /** Prefetcher */
76 Prefetcher<TagStore, Buffering> *prefetcher;
77 Prefetcher *prefetcher;
77
78 /**
79 * The clock ratio of the outgoing bus.
80 * Used for calculating critical word first.
81 */
82 int busRatio;
83
84 /**

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100 Request *invalidateReq;
101
102 public:
103
104 class Params
105 {
106 public:
107 TagStore *tags;
78
79 /**
80 * The clock ratio of the outgoing bus.
81 * Used for calculating critical word first.
82 */
83 int busRatio;
84
85 /**

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101 Request *invalidateReq;
102
103 public:
104
105 class Params
106 {
107 public:
108 TagStore *tags;
108 Buffering *missQueue;
109 MissBuffer *missQueue;
109 Coherence *coherence;
110 BaseCache::Params baseParams;
110 Coherence *coherence;
111 BaseCache::Params baseParams;
111 Prefetcher<TagStore, Buffering> *prefetcher;
112 Prefetcher *prefetcher;
112 bool prefetchAccess;
113 int hitLatency;
114
113 bool prefetchAccess;
114 int hitLatency;
115
115 Params(TagStore *_tags, Buffering *mq, Coherence *coh,
116 Params(TagStore *_tags, MissBuffer *mq, Coherence *coh,
116 BaseCache::Params params,
117 BaseCache::Params params,
117 Prefetcher<TagStore, Buffering> *_prefetcher,
118 Prefetcher *_prefetcher,
118 bool prefetch_access, int hit_latency)
119 : tags(_tags), missQueue(mq), coherence(coh),
120 baseParams(params),
121 prefetcher(_prefetcher), prefetchAccess(prefetch_access),
122 hitLatency(hit_latency)
123 {
124 }
125 };

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120 : tags(_tags), missQueue(mq), coherence(coh),
121 baseParams(params),
122 prefetcher(_prefetcher), prefetchAccess(prefetch_access),
123 hitLatency(hit_latency)
124 {
125 }
126 };

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