cache.hh (3293:4ac3d9486d6e) cache.hh (3315:f15ce6434ab0)
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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70 /** Miss and Writeback handler */
71 Buffering *missQueue;
72 /** Coherence protocol. */
73 Coherence *coherence;
74
75 /** Prefetcher */
76 Prefetcher<TagStore, Buffering> *prefetcher;
77
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 61 unchanged lines hidden (view full) ---

70 /** Miss and Writeback handler */
71 Buffering *missQueue;
72 /** Coherence protocol. */
73 Coherence *coherence;
74
75 /** Prefetcher */
76 Prefetcher<TagStore, Buffering> *prefetcher;
77
78 /** Do fast copies in this cache. */
79 bool doCopy;
80
81 /** Block on a delayed copy. */
82 bool blockOnCopy;
83
84 /**
85 * The clock ratio of the outgoing bus.
86 * Used for calculating critical word first.
87 */
88 int busRatio;
89
90 /**
91 * The bus width in bytes of the outgoing bus.

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100
101 /**
102 * A permanent mem req to always be used to cause invalidations.
103 * Used to append to target list, to cause an invalidation.
104 */
105 Packet * invalidatePkt;
106 Request *invalidateReq;
107
78 /**
79 * The clock ratio of the outgoing bus.
80 * Used for calculating critical word first.
81 */
82 int busRatio;
83
84 /**
85 * The bus width in bytes of the outgoing bus.

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94
95 /**
96 * A permanent mem req to always be used to cause invalidations.
97 * Used to append to target list, to cause an invalidation.
98 */
99 Packet * invalidatePkt;
100 Request *invalidateReq;
101
108 /**
109 * Temporarily move a block into a MSHR.
110 * @todo Remove this when LSQ/SB are fixed and implemented in memtest.
111 */
112 void pseudoFill(Addr addr);
113
114 /**
115 * Temporarily move a block into an existing MSHR.
116 * @todo Remove this when LSQ/SB are fixed and implemented in memtest.
117 */
118 void pseudoFill(MSHR *mshr);
119
120 public:
121
122 class Params
123 {
124 public:
125 TagStore *tags;
126 Buffering *missQueue;
127 Coherence *coherence;
102 public:
103
104 class Params
105 {
106 public:
107 TagStore *tags;
108 Buffering *missQueue;
109 Coherence *coherence;
128 bool doCopy;
129 bool blockOnCopy;
130 BaseCache::Params baseParams;
131 Prefetcher<TagStore, Buffering> *prefetcher;
132 bool prefetchAccess;
133 int hitLatency;
134
135 Params(TagStore *_tags, Buffering *mq, Coherence *coh,
110 BaseCache::Params baseParams;
111 Prefetcher<TagStore, Buffering> *prefetcher;
112 bool prefetchAccess;
113 int hitLatency;
114
115 Params(TagStore *_tags, Buffering *mq, Coherence *coh,
136 bool do_copy, BaseCache::Params params,
116 BaseCache::Params params,
137 Prefetcher<TagStore, Buffering> *_prefetcher,
138 bool prefetch_access, int hit_latency)
117 Prefetcher<TagStore, Buffering> *_prefetcher,
118 bool prefetch_access, int hit_latency)
139 : tags(_tags), missQueue(mq), coherence(coh), doCopy(do_copy),
140 blockOnCopy(false), baseParams(params),
119 : tags(_tags), missQueue(mq), coherence(coh),
120 baseParams(params),
141 prefetcher(_prefetcher), prefetchAccess(prefetch_access),
142 hitLatency(hit_latency)
143 {
144 }
145 };
146
147 /** Instantiates a basic cache object. */
148 Cache(const std::string &_name, Params &params);

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187
188 /**
189 * Handles a response (cache line fill/write ack) from the bus.
190 * @param pkt The request being responded to.
191 */
192 void handleResponse(Packet * &pkt);
193
194 /**
121 prefetcher(_prefetcher), prefetchAccess(prefetch_access),
122 hitLatency(hit_latency)
123 {
124 }
125 };
126
127 /** Instantiates a basic cache object. */
128 Cache(const std::string &_name, Params &params);

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167
168 /**
169 * Handles a response (cache line fill/write ack) from the bus.
170 * @param pkt The request being responded to.
171 */
172 void handleResponse(Packet * &pkt);
173
174 /**
195 * Start handling a copy transaction.
196 * @param pkt The copy request to perform.
197 */
198 void startCopy(Packet * &pkt);
199
200 /**
201 * Handle a delayed copy transaction.
202 * @param pkt The delayed copy request to continue.
203 * @param addr The address being responded to.
204 * @param blk The block of the current response.
205 * @param mshr The mshr being handled.
206 */
207 void handleCopy(Packet * &pkt, Addr addr, BlkType *blk, MSHR *mshr);
208
209 /**
210 * Selects a coherence message to forward to lower levels of the hierarchy.
211 * @return The coherence message to forward.
212 */
213 virtual Packet * getCoherencePacket();
214
215 /**
216 * Snoops bus transactions to maintain coherence.
217 * @param pkt The current bus transaction.

--- 59 unchanged lines hidden --- 		175 * Selects a coherence message to forward to lower levels of the hierarchy.
176 * @return The coherence message to forward.
177 */
178 virtual Packet * getCoherencePacket();
179
180 /**
181 * Snoops bus transactions to maintain coherence.
182 * @param pkt The current bus transaction.

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