cache.hh (2855:5ca2cdb32521) cache.hh (2982:0ecdb0879b14)
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 145 unchanged lines hidden (view full) ---

154 virtual void doFunctionalAccess(Packet *pkt, bool isCpuSide);
155
156 virtual void recvStatusChange(Port::Status status, bool isCpuSide);
157
158 void regStats();
159
160 /**
161 * Performs the access specified by the request.
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 145 unchanged lines hidden (view full) ---

154 virtual void doFunctionalAccess(Packet *pkt, bool isCpuSide);
155
156 virtual void recvStatusChange(Port::Status status, bool isCpuSide);
157
158 void regStats();
159
160 /**
161 * Performs the access specified by the request.
162 * @param req The request to perform.
162 * @param pkt The request to perform.
163 * @return The result of the access.
164 */
165 bool access(Packet * &pkt);
166
167 /**
168 * Selects a request to send on the bus.
169 * @return The memory request to service.
170 */
171 virtual Packet * getPacket();
172
173 /**
174 * Was the request was sent successfully?
163 * @return The result of the access.
164 */
165 bool access(Packet * &pkt);
166
167 /**
168 * Selects a request to send on the bus.
169 * @return The memory request to service.
170 */
171 virtual Packet * getPacket();
172
173 /**
174 * Was the request was sent successfully?
175 * @param req The request.
175 * @param pkt The request.
176 * @param success True if the request was sent successfully.
177 */
178 virtual void sendResult(Packet * &pkt, bool success);
179
180 /**
181 * Handles a response (cache line fill/write ack) from the bus.
176 * @param success True if the request was sent successfully.
177 */
178 virtual void sendResult(Packet * &pkt, bool success);
179
180 /**
181 * Handles a response (cache line fill/write ack) from the bus.
182 * @param req The request being responded to.
182 * @param pkt The request being responded to.
183 */
184 void handleResponse(Packet * &pkt);
185
186 /**
187 * Start handling a copy transaction.
183 */
184 void handleResponse(Packet * &pkt);
185
186 /**
187 * Start handling a copy transaction.
188 * @param req The copy request to perform.
188 * @param pkt The copy request to perform.
189 */
190 void startCopy(Packet * &pkt);
191
192 /**
193 * Handle a delayed copy transaction.
189 */
190 void startCopy(Packet * &pkt);
191
192 /**
193 * Handle a delayed copy transaction.
194 * @param req The delayed copy request to continue.
194 * @param pkt The delayed copy request to continue.
195 * @param addr The address being responded to.
196 * @param blk The block of the current response.
197 * @param mshr The mshr being handled.
198 */
199 void handleCopy(Packet * &pkt, Addr addr, BlkType *blk, MSHR *mshr);
200
201 /**
202 * Selects a coherence message to forward to lower levels of the hierarchy.
203 * @return The coherence message to forward.
204 */
205 virtual Packet * getCoherencePacket();
206
207 /**
208 * Snoops bus transactions to maintain coherence.
195 * @param addr The address being responded to.
196 * @param blk The block of the current response.
197 * @param mshr The mshr being handled.
198 */
199 void handleCopy(Packet * &pkt, Addr addr, BlkType *blk, MSHR *mshr);
200
201 /**
202 * Selects a coherence message to forward to lower levels of the hierarchy.
203 * @return The coherence message to forward.
204 */
205 virtual Packet * getCoherencePacket();
206
207 /**
208 * Snoops bus transactions to maintain coherence.
209 * @param req The current bus transaction.
209 * @param pkt The current bus transaction.
210 */
211 void snoop(Packet * &pkt);
212
213 void snoopResponse(Packet * &pkt);
214
215 /**
216 * Invalidates the block containing address if found.
217 * @param addr The address to look for.
218 * @param asid The address space ID of the address.
219 * @todo Is this function necessary?
220 */
221 void invalidateBlk(Addr addr, int asid);
222
223 /**
210 */
211 void snoop(Packet * &pkt);
212
213 void snoopResponse(Packet * &pkt);
214
215 /**
216 * Invalidates the block containing address if found.
217 * @param addr The address to look for.
218 * @param asid The address space ID of the address.
219 * @todo Is this function necessary?
220 */
221 void invalidateBlk(Addr addr, int asid);
222
223 /**
224 * Aquash all requests associated with specified thread.
224 * Squash all requests associated with specified thread.
225 * intended for use by I-cache.
225 * intended for use by I-cache.
226 * @param req->getThreadNum()ber The thread to squash.
226 * @param threadNum The thread to squash.
227 */
228 void squash(int threadNum)
229 {
230 missQueue->squash(threadNum);
231 }
232
233 /**
234 * Return the number of outstanding misses in a Cache.

--- 6 unchanged lines hidden (view full) ---

241 return missQueue->getMisses();
242 }
243
244 /**
245 * Perform the access specified in the request and return the estimated
246 * time of completion. This function can either update the hierarchy state
247 * or just perform the access wherever the data is found depending on the
248 * state of the update flag.
227 */
228 void squash(int threadNum)
229 {
230 missQueue->squash(threadNum);
231 }
232
233 /**
234 * Return the number of outstanding misses in a Cache.

--- 6 unchanged lines hidden (view full) ---

241 return missQueue->getMisses();
242 }
243
244 /**
245 * Perform the access specified in the request and return the estimated
246 * time of completion. This function can either update the hierarchy state
247 * or just perform the access wherever the data is found depending on the
248 * state of the update flag.
249 * @param req The memory request to satisfy
249 * @param pkt The memory request to satisfy
250 * @param update If true, update the hierarchy, otherwise just perform the
251 * request.
252 * @return The estimated completion time.
253 */
254 Tick probe(Packet * &pkt, bool update);
255
256 /**
257 * Snoop for the provided request in the cache and return the estimated
258 * time of completion.
259 * @todo Can a snoop probe not change state?
250 * @param update If true, update the hierarchy, otherwise just perform the
251 * request.
252 * @return The estimated completion time.
253 */
254 Tick probe(Packet * &pkt, bool update);
255
256 /**
257 * Snoop for the provided request in the cache and return the estimated
258 * time of completion.
259 * @todo Can a snoop probe not change state?
260 * @param req The memory request to satisfy
260 * @param pkt The memory request to satisfy
261 * @param update If true, update the hierarchy, otherwise just perform the
262 * request.
263 * @return The estimated completion time.
264 */
265 Tick snoopProbe(Packet * &pkt, bool update);
266};
267
268#endif // __CACHE_HH__
261 * @param update If true, update the hierarchy, otherwise just perform the
262 * request.
263 * @return The estimated completion time.
264 */
265 Tick snoopProbe(Packet * &pkt, bool update);
266};
267
268#endif // __CACHE_HH__