cache.hh (2826:d20db4a6f7d1) cache.hh (2844:265f19c60d45)
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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163 * @return The result of the access.
164 */
165 bool access(Packet * &pkt);
166
167 /**
168 * Selects a request to send on the bus.
169 * @return The memory request to service.
170 */
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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163 * @return The result of the access.
164 */
165 bool access(Packet * &pkt);
166
167 /**
168 * Selects a request to send on the bus.
169 * @return The memory request to service.
170 */
171 Packet * getPacket();
171 virtual Packet * getPacket();
172
173 /**
174 * Was the request was sent successfully?
175 * @param req The request.
176 * @param success True if the request was sent successfully.
177 */
178 void sendResult(Packet * &pkt, bool success);
179

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237 * @retval unsigned The number of missing still outstanding.
238 */
239 unsigned outstandingMisses() const
240 {
241 return missQueue->getMisses();
242 }
243
244 /**
172
173 /**
174 * Was the request was sent successfully?
175 * @param req The request.
176 * @param success True if the request was sent successfully.
177 */
178 void sendResult(Packet * &pkt, bool success);
179

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237 * @retval unsigned The number of missing still outstanding.
238 */
239 unsigned outstandingMisses() const
240 {
241 return missQueue->getMisses();
242 }
243
244 /**
245 * Send a response to the slave interface.
246 * @param req The request being responded to.
247 * @param time The time the response is ready.
248 */
249 void respond(Packet * &pkt, Tick time)
250 {
251 //si->respond(pkt,time);
252 cpuSidePort->sendAtomic(pkt);
253 }
254
255 /**
256 * Perform the access specified in the request and return the estimated
257 * time of completion. This function can either update the hierarchy state
258 * or just perform the access wherever the data is found depending on the
259 * state of the update flag.
260 * @param req The memory request to satisfy
261 * @param update If true, update the hierarchy, otherwise just perform the
262 * request.
263 * @return The estimated completion time.

--- 16 unchanged lines hidden --- 		245 * Perform the access specified in the request and return the estimated
246 * time of completion. This function can either update the hierarchy state
247 * or just perform the access wherever the data is found depending on the
248 * state of the update flag.
249 * @param req The memory request to satisfy
250 * @param update If true, update the hierarchy, otherwise just perform the
251 * request.
252 * @return The estimated completion time.

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