cache.hh (2812:8e5feae75615) cache.hh (2813:89d9196456ac)
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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39#define __CACHE_HH__
40
41#include "base/misc.hh" // fatal, panic, and warn
42#include "cpu/smt.hh" // SMT_MAX_THREADS
43
44#include "mem/cache/base_cache.hh"
45#include "mem/cache/prefetch/prefetcher.hh"
46
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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39#define __CACHE_HH__
40
41#include "base/misc.hh" // fatal, panic, and warn
42#include "cpu/smt.hh" // SMT_MAX_THREADS
43
44#include "mem/cache/base_cache.hh"
45#include "mem/cache/prefetch/prefetcher.hh"
46
47// forward declarations
48class Bus;
47//Forward decleration
48class MSHR;
49
49
50
50/**
51 * A template-policy based cache. The behavior of the cache can be altered by
52 * supplying different template policies. TagStore handles all tag and data
53 * storage @sa TagStore. Buffering handles all misses and writes/writebacks
54 * @sa MissQueue. Coherence handles all coherence policy details @sa
55 * UniCoherence, SimpleMultiCoherence.
56 */
57template <class TagStore, class Buffering, class Coherence>

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87 int busRatio;
88
89 /**
90 * The bus width in bytes of the outgoing bus.
91 * Used for calculating critical word first.
92 */
93 int busWidth;
94
51/**
52 * A template-policy based cache. The behavior of the cache can be altered by
53 * supplying different template policies. TagStore handles all tag and data
54 * storage @sa TagStore. Buffering handles all misses and writes/writebacks
55 * @sa MissQueue. Coherence handles all coherence policy details @sa
56 * UniCoherence, SimpleMultiCoherence.
57 */
58template <class TagStore, class Buffering, class Coherence>

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88 int busRatio;
89
90 /**
91 * The bus width in bytes of the outgoing bus.
92 * Used for calculating critical word first.
93 */
94 int busWidth;
95
96 /**
97 * The latency of a hit in this device.
98 */
99 int hitLatency;
100
95 /**
96 * A permanent mem req to always be used to cause invalidations.
97 * Used to append to target list, to cause an invalidation.
98 */
99 Packet * invalidatePkt;
100
101 /**
102 * Temporarily move a block into a MSHR.

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116 {
117 public:
118 TagStore *tags;
119 Buffering *missQueue;
120 Coherence *coherence;
121 bool doCopy;
122 bool blockOnCopy;
123 BaseCache::Params baseParams;
101 /**
102 * A permanent mem req to always be used to cause invalidations.
103 * Used to append to target list, to cause an invalidation.
104 */
105 Packet * invalidatePkt;
106
107 /**
108 * Temporarily move a block into a MSHR.

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122 {
123 public:
124 TagStore *tags;
125 Buffering *missQueue;
126 Coherence *coherence;
127 bool doCopy;
128 bool blockOnCopy;
129 BaseCache::Params baseParams;
124 Bus *in;
125 Bus *out;
126 Prefetcher<TagStore, Buffering> *prefetcher;
127 bool prefetchAccess;
130 Prefetcher<TagStore, Buffering> *prefetcher;
131 bool prefetchAccess;
132 int hitLatency;
128
129 Params(TagStore *_tags, Buffering *mq, Coherence *coh,
133
134 Params(TagStore *_tags, Buffering *mq, Coherence *coh,
130 bool do_copy, BaseCache::Params params, Bus * in_bus,
131 Bus * out_bus, Prefetcher<TagStore, Buffering> *_prefetcher,
132 bool prefetch_access)
135 bool do_copy, BaseCache::Params params,
136 Prefetcher *_prefetcher,
137 bool prefetch_access, int hit_latency)
133 : tags(_tags), missQueue(mq), coherence(coh), doCopy(do_copy),
138 : tags(_tags), missQueue(mq), coherence(coh), doCopy(do_copy),
134 blockOnCopy(false), baseParams(params), in(in_bus), out(out_bus),
135 prefetcher(_prefetcher), prefetchAccess(prefetch_access)
139 blockOnCopy(false), baseParams(params),
140 prefetcher(_prefetcher), prefetchAccess(prefetch_access),
141 hitLatency(hit_latency)
136 {
137 }
138 };
139
140 /** Instantiates a basic cache object. */
141 Cache(const std::string &_name, Params &params);
142
142 {
143 }
144 };
145
146 /** Instantiates a basic cache object. */
147 Cache(const std::string &_name, Params &params);
148
149 bool doTimingAccess(Packet *pkt, CachePort *cachePort,
150 bool isCpuSide);
151
152 Tick doAtomicAccess(Packet *pkt, CachePort *cachePort,
153 bool isCpuSide);
154
155 void doFunctionalAccess(Packet *pkt, CachePort *cachePort,
156 bool isCpuSide);
157
158 void recvStatusChange(Port::Status status, bool isCpuSide);
159
143 void regStats();
144
145 /**
146 * Performs the access specified by the request.
147 * @param req The request to perform.
148 * @return The result of the access.
149 */
150 bool access(Packet * &pkt);

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161
162 /**
163 * Performs the access specified by the request.
164 * @param req The request to perform.
165 * @return The result of the access.
166 */
167 bool access(Packet * &pkt);

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